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1. 发明授权

US08140759B2 Specifying an access hint for prefetching partial cache block data in a cache hierarchy 失效
标题翻译：指定用于在缓存层次结构中预取部分高速缓存块数据的访问提示
公开(公告)号：US08140759B2
公开(公告)日：2012-03-20
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

2. 发明申请

US20100268886A1 SPECIFYING AN ACCESS HINT FOR PREFETCHING PARTIAL CACHE BLOCK DATA IN A CACHE HIERARCHY 失效
标题翻译：指定访问提示用于缓存高速缓存中的部分缓存块数据
公开(公告)号：US20100268886A1
公开(公告)日：2010-10-21
申请号：US12424716
申请日：2009-04-16
申请人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
发明人： Bradly George Frey , Guy Lynn Guthrie , Cathy May , Ramakrishnan Rajamony , Balaram Sinharoy , William John Starke , Peter Kenneth Szwed
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0817 , G06F2212/6028
摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.
摘要翻译：用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

3. 发明授权

US07996564B2 Remote asynchronous data mover 失效
标题翻译：远程异步数据移动器
公开(公告)号：US07996564B2
公开(公告)日：2011-08-09
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译：分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问数据中心为远程存储器的节点ID。

4. 发明申请

US20100268788A1 Remote Asynchronous Data Mover 失效
标题翻译：远程异步数据移动器
公开(公告)号：US20100268788A1
公开(公告)日：2010-10-21
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F15/167 , G06F9/46 , G06F12/00 , G06F12/10
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译：分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问数据中心为远程存储器的节点ID。

5. 发明申请

US20060080506A1 Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing 失效
标题翻译：多处理器NUCA系统中的数据复制，以减少水平缓存的颠簸
公开(公告)号：US20060080506A1
公开(公告)日：2006-04-13
申请号：US10960611
申请日：2004-10-07
申请人： Ramakrishnan Rajamony , Xiaowei Shen , Balaram Sinharoy
发明人： Ramakrishnan Rajamony , Xiaowei Shen , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0813 , G06F12/084 , G06F12/122 , G06F2212/271
摘要： A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache, and replicating that cache line in at least two separate cache banks. The cache line is optimally replicated in a cache bank having the lowest latency with respect to the given accessing processor. A currently accessed line in a different cache bank can be exchanged with a cache line in the cache bank with the lowest latency, and another line in the cache bank with lowest latency is moved to the different cache bank prior to the currently accessed line being moved to the cache bank with the lowest latency. Further replication of the cache line can be disabled when two or more processors alternately write to the cache line.
摘要翻译：一种通过检测给定的高速缓存行已被共享高速缓存的两个或多个处理器重复访问并且在至少两个单独的高速缓冲存储器中复制该高速缓存行的方式来管理具有单独的高速缓存组的分布式高速缓存结构的方法。高速缓存行被优化地复制到相对于给定访问处理器具有最低延迟的缓存组中。在不同的缓存组中的当前访问的行可以与具有最低延迟的高速缓存组中的高速缓存行交换，并且具有最低延迟的高速缓存组中的另一行在当前访问的行被移动之前移动到不同的高速缓存组以最低的延迟到达缓存库。当两个或更多个处理器交替写入高速缓存行时，可以禁用高速缓存行的进一步复制。

6. 发明申请

US20120198459A1 ASSIST THREAD FOR INJECTING CACHE MEMORY IN A MICROPROCESSOR 有权
标题翻译：在微处理器中注入高速缓存存储器的辅助螺纹
公开(公告)号：US20120198459A1
公开(公告)日：2012-08-02
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

7. 发明授权

US08230422B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08230422B2
公开(公告)日：2012-07-24
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F9/40 , G06F13/28
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

8. 发明授权

US08949837B2 Assist thread for injecting cache memory in a microprocessor 有权
标题翻译：协助在微处理器中注入高速缓存的线程
公开(公告)号：US08949837B2
公开(公告)日：2015-02-03
申请号：US13434423
申请日：2012-03-29
申请人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
发明人： Patrick Joseph Bohrer , Orran Yaakov Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Brett Tremaine
IPC分类号： G06F9/46 , G06F12/00 , G06F9/38 , G06F12/08 , G06F9/48
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
摘要翻译：数据处理系统包括具有访问多级缓存存储器的微处理器。微处理器执行从源代码对象编译的主线程。该系统包括用于执行也源自源代码对象的辅助线程的处理器。辅助线程包括主线程的存储器参考指令和仅解析存储器参考指令所需的算术指令。配置成与对应的执行线程一起调度辅助线程的调度器被配置为通过诸如主处理器周期的数量或代码指令的数量的可确定的阈值来执行执行线程之前的辅助线程。辅助线程可以在主处理器或专用辅助处理器中执行，该处理器直接对下一级高速缓冲存储器元件之一进行存储器访问。

9. 发明授权

US07287122B2 Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing 失效
标题翻译：多处理器NUCA系统中的数据复制，以减少水平缓存的颠簸
公开(公告)号：US07287122B2
公开(公告)日：2007-10-23
申请号：US10960611
申请日：2004-10-07
申请人： Ramakrishnan Rajamony , Xiaowei Shen , Balaram Sinharoy
发明人： Ramakrishnan Rajamony , Xiaowei Shen , Balaram Sinharoy
IPC分类号： G06F15/163 , G06F13/36
CPC分类号： G06F12/0846 , G06F12/0813 , G06F12/084 , G06F12/122 , G06F2212/271
摘要： A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache, and replicating that cache line in at least two separate cache banks. The cache line is optimally replicated in a cache bank having the lowest latency with respect to the given accessing processor. A currently accessed line in a different cache bank can be exchanged with a cache line in the cache bank with the lowest latency, and another line in the cache bank with lowest latency is moved to the different cache bank prior to the currently accessed line being moved to the cache bank with the lowest latency. Further replication of the cache line can be disabled when two or more processors alternately write to the cache line.
摘要翻译：一种通过检测给定的高速缓存行已被共享高速缓存的两个或多个处理器重复访问并且在至少两个单独的高速缓冲存储器中复制该高速缓存行的方式来管理具有单独的高速缓存组的分布式高速缓存结构的方法。高速缓存行被优化地复制到相对于给定访问处理器具有最低延迟的缓存组中。在不同的缓存组中的当前访问的行可以与具有最低延迟的高速缓存组中的高速缓存行交换，并且具有最低延迟的高速缓存组中的另一行在当前访问的行被移动之前移动到不同的高速缓存组以最低的延迟到达缓存库。当两个或更多个处理器交替写入高速缓存行时，可以禁用高速缓存行的进一步复制。

10. 发明申请

US20060155963A1 Assist thread for injecting cache memory in a microprocessor 有权
公开(公告)号：US20060155963A1
公开(公告)日：2006-07-13
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Bohrer , Orran Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Tremaine
发明人： Patrick Bohrer , Orran Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Tremaine
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

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