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1. 发明授权

US09047079B2 Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition 有权
标题翻译：当竞争性指令完成执行以确保安全的共享资源状况时，指示禁用线程到其他线程
公开(公告)号：US09047079B2
公开(公告)日：2015-06-02
申请号：US13435123
申请日：2012-03-30
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3889
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

2. 发明申请

US20120185678A1 HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION 有权
标题翻译：硬件螺纹与状态指示安全共享资源条件
公开(公告)号：US20120185678A1
公开(公告)日：2012-07-19
申请号：US13435123
申请日：2012-03-30
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857 , G06F9/3889
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

3. 发明申请

US20110208949A1 HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION 有权
标题翻译：硬件螺纹与状态指示安全共享资源条件
公开(公告)号：US20110208949A1
公开(公告)日：2011-08-25
申请号：US12708791
申请日：2010-02-19
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

4. 发明授权

US08615644B2 Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition 有权
标题翻译：具有硬件线程控制逻辑的处理器，指示访问共享资源的指令在安全共享资源状态完成时指示禁用状态
公开(公告)号：US08615644B2
公开(公告)日：2013-12-24
申请号：US12708791
申请日：2010-02-19
申请人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
发明人： Becky Bruce , Giles R. Frazier , Bradly G. Frey , Kumar K. Gala , Cathy May , Michael D. Snyder , Gary Whisenhunt , James Xenidis
IPC分类号： G06F9/38
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3857
摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.
摘要翻译：用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找，处理器核心内的缓冲区。来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。然后控制逻辑更新线程状态以指示线程被禁用。

5. 发明授权

US09395983B2 Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation 有权
标题翻译：调试指令由第一个线程执行以在第二个线程中生成调试事件以导致暂停操作
公开(公告)号：US09395983B2
公开(公告)日：2016-07-19
申请号：US12195220
申请日：2008-08-20
申请人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
发明人： William C. Moyer , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30 , G06F11/36
CPC分类号： G06F9/3005 , G06F9/3009 , G06F11/3648
摘要： For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.
摘要翻译：为了在包括处理器的数据处理系统中使用，该处理器被配置为执行对应于第一线程的第一组指令和对应于第二线程的第二组指令，提供了一种方法。该方法包括响应于在执行第一组指令时由第一线程执行与调试相关的指令，生成用于由第二线程处理的调试事件，其中处理调试事件包括引起与处理器相关的暂停操作。

6. 发明授权

US08531899B2 Methods for testing a memory embedded in an integrated circuit 有权
标题翻译：测试嵌入在集成电路中的存储器的方法
公开(公告)号：US08531899B2
公开(公告)日：2013-09-10
申请号：US13613630
申请日：2012-09-13
申请人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译：存储器系统具有包括冗余列的存储器单元阵列的第一存储器。冗余列代替数组中的第一列。第一列包括测试存储单元。阵列接收电源电压。测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。这对于对应用于阵列的电源电压的值做出决定是有用的。

7. 发明授权

US08380779B2 Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand 有权
标题翻译：用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术
公开(公告)号：US08380779B2
公开(公告)日：2013-02-19
申请号：US12474451
申请日：2009-05-29
申请人： Klas M. Bruce , Michael D. Snyder , Ravindraraj Ramaraju , David R. Bearden
发明人： Klas M. Bruce , Michael D. Snyder , Ravindraraj Ramaraju , David R. Bearden
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译：系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。通过参考以下描述和附图可以更好地理解这一点。

8. 发明授权

US08379466B2 Integrated circuit having an embedded memory and method for testing the memory 有权
标题翻译：具有嵌入式存储器的集成电路和用于测试存储器的方法
公开(公告)号：US08379466B2
公开(公告)日：2013-02-19
申请号：US12414758
申请日：2009-03-31
申请人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译：存储器系统具有包括冗余列的存储器单元阵列的第一存储器。冗余列替代数组中的第一列。第一列包括测试存储单元。阵列接收电源电压。测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。这对于对应用于阵列的电源电压的值做出决定是有用的。

9. 发明授权

US08199547B2 Error detection in a content addressable memory (CAM) 有权
标题翻译：内容可寻址存储器（CAM）中的错误检测
公开(公告)号：US08199547B2
公开(公告)日：2012-06-12
申请号：US12703528
申请日：2010-02-10
申请人： Ravindraraj Ramaraju , Michael D. Snyder
发明人： Ravindraraj Ramaraju , Michael D. Snyder
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F11/1064 , G11C29/52
摘要： A content addressable memory and method of operation uses a memory array having a plurality of rows of stored content addressable memory data and compare circuitry for comparing received comparand data with the stored content addressable memory data. A hit signal and one or more parity bits is provided for each row. Erroneous hit detection circuitry coupled to the memory array for each row generates a row error indicator in response to a comparison between parity of the comparand data and parity of a row that is correlated to the hit signal as qualified by assertion of a hit signal of that row. The erroneous hit detection circuitry uses the row error indicator for each row to provide an output which indicates whether at least one asserted hit signal corresponds to an erroneous hit.
摘要翻译：内容可寻址存储器和操作方法使用具有多行存储的内容可寻址存储器数据的存储器阵列和用于将接收到的比较数据与存储的内容可寻址存储器数据进行比较的比较电路。为每行提供命中信号和一个或多个奇偶校验位。耦合到每行的存储器阵列的错误的命中检测电路响应于比较数据的奇偶性与与命中信号相关联的行的奇偶校验之间的比较，产生行错误指示，如通过断言该命中信号的命中信号行。错误的命中检测电路使用每一行的行错误指示符来提供指示至少一个被断言的命中信号是否对应于错误命中的输出。

10. 发明授权

US08122437B2 Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors 有权
标题翻译：跟踪和关联无序处理器的数据跟踪和指令跟踪的方法和装置
公开(公告)号：US08122437B2
公开(公告)日：2012-02-21
申请号：US12058874
申请日：2008-03-31
申请人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
发明人： Zheng Xu , Suraj Bhaskaran , Klas M. Bruce , Jason T. Nearing , Paul B. Rawlins , Matt B. Smittle , Michael D. Snyder
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/3636
摘要： In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.
摘要翻译：在数据处理系统中，使用标记位来标识整个流水线中的数据访问指令，以指示该指令满足用户指定的标准（例如，满足感兴趣的数据地址范围）。基于标记位，产生一个顺序程序相关消息，指示何时相对于指令流发生数据访问指令。标记位还用于生成按顺序数据跟踪消息。因此，仅包括满足用户指定标准的数据访问指令的跟踪流可以被后处理并且精确地相关联。

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