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1. 发明授权

US4760517A Thirty-two bit, bit slice processor 失效
标题翻译：三十二位，位片处理器
公开(公告)号：US4760517A
公开(公告)日：1988-07-26
申请号：US920716
申请日：1986-10-17
申请人： Michael J. Miller , Danh Le Ngoc , John R. Mick
发明人： Michael J. Miller , Danh Le Ngoc , John R. Mick
IPC分类号： G06F9/22 , G06F7/00 , G06F7/57 , G06F15/78 , G06F9/00
CPC分类号： G06F15/7896
摘要： The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.
摘要翻译：配置七端口随机存取存储器（RAM）单元，漏斗移位器，掩码发生器，算术逻辑单元（ALU），合并逻辑单元，多个复用器和三个双向数据总线的组合形成三十二位，可级联，可编程的位片，适用于执行复杂的操作，例如那些需要从存储器单元读取多个操作数的操作数，在漏斗移位器中旋转，由算术逻辑单元，合并到合并逻辑单元中，结果将在单个周期内写入存储器单元。

2. 发明授权

US5175819A Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer 失效
标题翻译：使用抽头移位寄存器和数据移位寄存器并行串行转换器，同时从FIFO缓冲区接收输入数据
公开(公告)号：US5175819A
公开(公告)日：1992-12-29
申请号：US500678
申请日：1990-03-28
申请人： Danh Le Ngoc , Fulam Au , John R. Mick
发明人： Danh Le Ngoc , Fulam Au , John R. Mick
IPC分类号： G06F5/06 , H03M9/00
CPC分类号： H03M9/00 , G06F5/06
摘要： A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.
摘要翻译：并行到串行FIFO缓冲器（100）使用用于存储数据字的FIFO缓冲器（110）抽头移位寄存器部分（112）; 以及用于从存储在FIFO缓冲器（110）中的数据的并行转换为串行格式字的数据移位寄存器部分（116），抽头移位寄存器部分（112）控制转换处理，接收（150）串行输入扩展（RSIX）输入信号，并开发（170）串行输出扩展（RSOX）输出信号。串行输入扩展输入信号（150）和串行输出扩展输出信号（170）允许设备（100）与一个或多个相似的用于字长和/或相似的设备连接，深度扩张。

3. 发明授权

US4931974A Sixteen-bit programmable pipelined arithmetic logic unit 失效
标题翻译：十六位可编程流水线算术逻辑单元
公开(公告)号：US4931974A
公开(公告)日：1990-06-05
申请号：US304069
申请日：1989-01-30
申请人： Danh Le Ngoc , John R. Mick
发明人： Danh Le Ngoc , John R. Mick
IPC分类号： G06F7/00 , G06F7/57 , G06F17/10 , G06F17/14
CPC分类号： G06F7/57 , G06F17/142 , G06F2207/3884 , G06F7/49947
摘要： For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register ("A"), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and "delay" the parameter represented by the state of signals externally developed on a "DA" bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for "bit-reverse order" addressing; and a unit for "rounding off" certain results.

4. 发明授权

US4782461A Logical grouping of facilities within a computer development system 失效
标题翻译：计算机开发系统内的设施的逻辑分组
公开(公告)号：US4782461A
公开(公告)日：1988-11-01
申请号：US623160
申请日：1984-06-21
申请人： John R. Mick , Darrell L. Wilburn , Michael J. Miller
发明人： John R. Mick , Darrell L. Wilburn , Michael J. Miller
IPC分类号： G06F11/22 , G06F11/32 , G06F11/34 , G06F11/36 , G06F9/00
CPC分类号： G06F11/3652 , G06F11/322 , G06F11/22 , G06F11/34
摘要： A logical grouping of facilities within a computer development system where said facilities include breakpoint control, trace control and memory, a plurality of VLSI emulators, a plurality of storage device emulators, a plurality of emulators for simulating program or microprogram storage, and may be selectively assigned to said grouping by a user. Said selectively assigned facilities are associated with a clock control and are used for the design, debugging and testing of computer systems.
摘要翻译：计算机开发系统内的设备的逻辑分组，其中所述设施包括断点控制，跟踪控制和存储器，多个VLSI仿真器，多个存储设备仿真器，用于模拟程序或微程序存储的多个仿真器，并且可以是选择性地被用户分配给所述分组。所述选择性分配的设施与时钟控制相关联，并且用于计算机系统的设计，调试和测试。

5. 发明授权

US5331645A Expandable digital error detection and correction device 失效
标题翻译：可扩展数字错误检测和校正装置
公开(公告)号：US5331645A
公开(公告)日：1994-07-19
申请号：US54346
申请日：1993-04-26
申请人： Michael J. Miller , Andy P. Chan , Robert W. Stodieck , John R. Mick
发明人： Michael J. Miller , Andy P. Chan , Robert W. Stodieck , John R. Mick
IPC分类号： G06F11/10 , H03M13/19 , H03M13/00
CPC分类号： G06F11/1048 , H03M13/19
摘要： A pair of similar, 32-bit, error detection and correction devices, including a "lower 32-bit" device (210) and an "upper 32-bit" device (212) are configured as a 64-bit, error detection and correction system. When a (64-bit) word of data is being stored in memory, the lower 32-bit device (210) develops, on an inter-device bus (226), signals representing generation partial check bits. The upper 32-bit device (212) receives the partial check bits (226), and develops signals representing final check bits (236) for storage with the corresponding data word in memory (220 and 234). When a (64-bit) word of data is being retrieved from memory, from signals representing check bits retrieved from memory (222), the lower 32-bit device (210) generates on an inter-device bus (224), signals representing correction partial syndromes. From the correction partial syndromes (224), the upper 32-bit device (212) develops, on another inter-device bus (228), signals representing correction partial check bits; generates full syndromes; and corrects errors in the upper 32-bits of the corresponding retrieved data word (240). From the correction partial check bits (228) the lower 32-bit device (210) (also) generates full syndromes; and corrects errors in the corresponding lower 32-bits of the retrieved data word (230).
摘要翻译：包括“低32位”设备（210）和“高32位”设备（212）的一对类似的32位错误检测和校正设备被配置为64位错误检测和校正系统当存储器中存储（64位）数据字时，下位32位器件（210）在器件间总线（226）上产生表示生成部分校验位的信号。上部32位设备（212）接收部分校验位（226），并且产生表示用于与存储器（220和234）中的相应数据字存储的最终校验位（236）的信号。当从存储器检索到（64位）数据字时，从表示从存储器（222）检索的校验位的信号中，下部32位器件（210）在器件间总线（224）上产生信号，矫正部分综合征。从校正部分综合征（224），上部32位装置（212）在另一个装置间总线（228）上形成表示校正部分校验位的信号; 产生完整的综合征; 并纠正对应检索的数据字（240）的高32位的错误。从校正部分校验位（228），下部32位器件（210）（也）产生完整的校正子; 并纠正检索的数据字（230）的相应较低32位中的错误。

6. 发明授权

US5581564A Diagnostic circuit 失效
标题翻译：诊断电路
公开(公告)号：US5581564A
公开(公告)日：1996-12-03
申请号：US629285
申请日：1990-12-18
申请人： Michael J. Miller , John R. Mick
发明人： Michael J. Miller , John R. Mick
IPC分类号： G06F11/22 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/318572
摘要： A diagnostic circuit of the present invention has serial command input and output pins separate from its serial data input and output pins. In one embodiment, the diagnostic circuit has one command register and one data register, the data register receiving serially an input signal and providing serially an output signal through an input pin and an output pin respectively. In another embodiment, the diagnostic circuit has one command register and multiple data registers. Each data register including a zero-length register, can be separately addressed. In yet another embodiment, multiple serial data input and output pins are provided together with multiple data registers.
摘要翻译：本发明的诊断电路具有与其串行数据输入和输出引脚分开的串行命令输入和输出引脚。在一个实施例中，诊断电路具有一个命令寄存器和一个数据寄存器，数据寄存器串行地接收输入信号，并分别通过输入引脚和输出引脚提供输出信号。在另一个实施例中，诊断电路具有一个命令寄存器和多个数据寄存器。每个包括零长度寄存器的数据寄存器都可以单独寻址。在另一个实施例中，多个串行数据输入和输出引脚与多个数据寄存器一起提供。

7. 发明授权

US06470418B1 Pipelining a content addressable memory cell array for low-power operation 有权
标题翻译：内置可寻址存储单元阵列，用于低功耗操作
公开(公告)号：US06470418B1
公开(公告)日：2002-10-22
申请号：US09232413
申请日：1999-01-15
申请人： Chuen-Der Lien , Chau-Chin Wu , John R. Mick
发明人： Chuen-Der Lien , Chau-Chin Wu , John R. Mick
IPC分类号： G06F1200
CPC分类号： G06F17/30982 , G11C7/1039 , G11C15/00
摘要： A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.
摘要翻译：一种内容寻址存储器（CAM）系统，其包括分别产生具有较高和较低优先级的第一和第二组匹配控制信号的第一和第二CAM阵列。第一个CAM阵列在第一个存储器周期中被使能，并且分析第一组匹配控制信号。如果在第一CAM阵列中存在匹配，则使能第一优先级编码器来处理第一组匹配控制信号。如果不存在匹配，则不启用第一优先级编码器，并且启动第二存储器周期。第二个CAM阵列在第二个存储周期中被使能，第二组信号被分析。如果在第二CAM阵列中存在匹配，则使能第二优先级编码器来处理第二组匹配控制信号。如果不存在匹配，则不启用第二优先级编码器。

8. 发明授权

US06249480B1 Fully synchronous pipelined ram 有权
标题翻译：完全同步流水线冲压
公开(公告)号：US06249480B1
公开(公告)日：2001-06-19
申请号：US09429849
申请日：1999-10-28
申请人： John R. Mick
发明人： John R. Mick
IPC分类号： G11C800
CPC分类号： G11C7/1039 , G11C7/1072 , G11C2207/2218
摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
摘要翻译：存储器系统包括存储器，输入电路和逻辑电路。输入电路被耦合以接收存储器地址，并且在写入操作期间将相应的写入数据写入到SRAM中。逻辑电路使写入数据在写入操作之后立即在任何顺序读取操作期间存储在输入电路中，然后在随后的写入操作期间被读入存储器。在读取操作期间，如果一个或多个读取操作的地址等于要写入到存储器中的数据的地址，则可以从存储器系统读出在写入存储器之前存储在写入数据存储寄存器中的数据存储器，同时临时存储在写入数据存储寄存器中。因此，系统不会经历“总线周转”停机时间，从而增加了系统的带宽。系统可以在单管道模式或双管道模式下运行。

9. 发明授权

US6115320A Separate byte control on fully synchronous pipelined SRAM 失效
标题翻译：完全同步流水线SRAM上的单独字节控制
公开(公告)号：US6115320A
公开(公告)日：2000-09-05
申请号：US28206
申请日：1998-02-23
申请人： John R. Mick , Mark W. Baumann
发明人： John R. Mick , Mark W. Baumann
IPC分类号： G11C11/419 , G11C8/00
CPC分类号： G11C11/419
摘要： A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.
摘要翻译：提出了包括存储器阵列，输入电路和逻辑电路的存储器系统。输入电路被耦合以接收数据字的每个字节的存储器地址和一组单独的写入控制。在写入操作期间，输入电路还接收要写入SRAM的相应写入数据。逻辑电路使得写入数据和写入控制信息在写入操作之后的任何顺序读取操作期间存储在输入电路中，然后在随后的写入操作期间被读取到存储器中。在读取操作期间，如果一个或多个读取操作的地址等于要写入到存储器中的数据的地址，则可以从存储器系统读出在写入存储器之前存储在写入数据存储寄存器中的数据存储器，同时临时存储在写入数据存储寄存器中。

10. 发明授权

US5838631A Fully synchronous pipelined ram 失效
公开(公告)号：US5838631A
公开(公告)日：1998-11-17
申请号：US635128
申请日：1996-04-19
申请人： John R. Mick
发明人： John R. Mick
IPC分类号： G11C7/10 , G11C13/00
CPC分类号： G11C7/1039 , G11C7/1072 , G11C2207/2218
摘要： A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no "bus turnaround" down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

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