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    • 8. 发明授权
    • Mask-saving production of complementary lateral high-voltage transistors with a RESURF structure
    • 使用RESURF结构掩盖了生产互补的横向高压晶体管
    • US08207031B2
    • 2012-06-26
    • US12593310
    • 2008-03-26
    • Christoph EllmersThomas UhligFelix FuernhammerMichael StoisiekMichael Gross
    • Christoph EllmersThomas UhligFelix FuernhammerMichael StoisiekMichael Gross
    • H01L21/8238
    • H01L21/823807H01L21/823814H01L27/0922
    • Methods of forming, on a substrate, a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complementary to said first one are disclosed. According to one embodiment, the method includes (1) providing a substrate of a first conductivity type including a first active region for said first lateral high-voltage MOS transistor and a second active region for said second lateral high-voltage MOS transistor and (2) forming at least one first doped region of the first conductivity type in the first active region and forming in the second active region a drain extension region of the second conductivity type extending from a substrate surface to an interior of the substrate, including a concurrent implantation of dopants through openings of one and the same mask into the first and second active regions. Forming of the at least one first doped region may be a sub step of a superior step of forming a double RESURF structure in the first lateral high-voltage MOS transistor, and forming the double RESURF structure may include forming doped RESURF regions as two first doped regions, one thereof above and one thereof below the drift region of the first lateral high-voltage MOS transistor, and as two further doped regions, one thereof above and one thereof below the drain extension regions of the second lateral high-voltage MOS transistor, wherein the first doped RESURF regions have an inverse conductivity type with respect to the drift region and the further doped regions have inverse conductivity type as compared to the drain extension region.
    • 公开了在基板上形成与所述第一横向高压MOS晶体管和第二横向高压MOS晶体管互补的方法。 根据一个实施例,该方法包括(1)提供第一导电类型的衬底,其包括用于所述第一横向高压MOS晶体管的第一有源区和用于所述第二横向高压MOS晶体管的第二有源区和(2 )在所述第一有源区中形成所述第一导电类型的至少一个第一掺杂区域,并且在所述第二有源区域中形成从衬底表面延伸到所述衬底内部的所述第二导电类型的漏极延伸区域,所述漏极延伸区域包括同时植入 的掺杂剂通过同一掩模的开口进入第一和第二活性区域。 形成至少一个第一掺杂区域可以是在第一横向高压MOS晶体管中形成双重RESURF结构的优异步骤的子步骤,并且形成双重RESURF结构可以包括形成掺杂的RESURF区域作为两个第一掺杂 区域,其中一个位于第一横向高压MOS晶体管的漂移区以下,其中一个位于第二横向高压MOS晶体管的漏极延伸区之下,其中一个位于第二横向高压MOS晶体管的漏极延伸区之下, 其中所述第一掺杂RESURF区域相对于所述漂移区域具有反向导电类型,并且所述另外的掺杂区域与所述漏极延伸区域相比具有反向导电类型。
    • 9. 发明申请
    • OPERATING TEMPERATURE MEASUREMENT FOR AN MOS POWER COMPONENT, AND MOS COMPONENT FOR CARRYING OUT THE METHOD
    • MOS功率元件的运行温度测量和实现方法的MOS元件
    • US20110182324A1
    • 2011-07-28
    • US12993559
    • 2009-05-19
    • Michael StoisiekMichael Gross
    • Michael StoisiekMichael Gross
    • G01K7/26H01L23/58
    • G01K7/16G01K2217/00H01L29/42372H01L29/4238H01L29/7816H01L2924/0002H01L2924/00
    • The invention is intended to specify an electrical measuring method for an operating temperature and a modified component for carrying out the method which improves the monitoring of the component. Measured temperature values are intended to be delivered without any time delay and without requiring additional surfaces for temperature sensors. Location-related temperature values need to be able to be measured. The invention proposes a method for said location-related electrical measurement of the operating temperature of a likewise proposed MOS power component with a gate electrode network comprising a material whose temperature coefficient of the electrical resistance is known. The gate electrode network is divided into a plurality of measuring sections with contact point pairs which are respectively connected to contacts (71.1, 72.1; 71.2, 72.2; 71.3, 7; 72.3, 7). The contact points in each contact point pair are at a certain distance from one another, and each of the measuring sections situated between the contact point pairs is respectively electrically insulated from the other measuring sections, so that there is no electrical influencing between the measuring sections. The electrical resistances of the measuring sections are measured directly on the gate electrode network during the operation of the semiconductor power component when gate voltages are applied between the contact points of the gate electrode (4) using measuring voltages (u1, u2, u3) superimposed on the gate voltages. The electrical resistances of the measuring sections are used to determine the temperatures of the MOS semiconductor power component on the measuring sections.
    • 本发明旨在指定用于操作温度的电测量方法和用于实施改进对部件的监视的方法的改进部件。 测量的温度值意图在没有任何时间延迟的情况下传送,而不需要额外的温度传感器表面。 需要测量位置相关的温度值。 本发明提出了一种用于所述位置相关电测量同样提出的MOS功率部件的操作温度的方法,其中栅电极网络包括其电阻温度系数已知的材料。 栅极电极网络被分成多个测量部分,其具有分别连接到触点(71.1,72.1; 71.2,72.2; 71.3,7,72.3,7)的接触点对。 每个接触点对中的接触点彼此距离一定距离,并且位于接触点对之间的每个测量部分分别与其它测量部分电绝缘,使得在测量部分 。 在使用测量电压(u1,u2,u3)叠加的栅电极(4)的接触点之间施加栅极电压时,在半导体功率分量的运行期间,在栅电极网络上直接测量测量部分的电阻 对栅极电压。 测量部分的电阻用于确定测量部分上的MOS半导体功率部件的温度。