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1. 发明授权

US08060800B2 Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn 有权
标题翻译：用于检测和/或定位数据流Tn中的故障数据字的评估电路和方法
公开(公告)号：US08060800B2
公开(公告)日：2011-11-15
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流Tn的公共输入线。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

2. 发明申请

US20080040638A1 Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn 有权
标题翻译：用于检测和/或定位数据流中的故障数据字的评估电路和方法
公开(公告)号：US20080040638A1
公开(公告)日：2008-02-14
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G06F11/22
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流T n 。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

3. 发明申请

US20070089010A1 Test apparatus for digitized test responses, method for testing semiconductor devices and diagnosis method for a semiconductor device 有权
标题翻译：用于数字化测试响应的测试装置，半导体器件测试方法和半导体器件的诊断方法
公开(公告)号：US20070089010A1
公开(公告)日：2007-04-19
申请号：US11534005
申请日：2006-09-21
申请人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
发明人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318371 , H03M1/1085 , H03M1/12
摘要： A test apparatus for testing digitized test responses has a generator (2) and a signal extractor (3). The generator (2) uses direct digital synthesis to generate a set of n digital reference signals (xk, yk) which are orthogonal to one another. In this case, n is a natural number greater than 1. The signal extractor (3) contains a test input and a plurality of reference inputs. The test input receives a digitized test response (E) and the reference inputs are connected to the reference signals (xk, yk) which are generated by the generator (2). The signal extractor (3) generates scalar products from a respective reference signal (xk, yk) and the test response (E) and uses said products to calculate whether a combination of reference signals (xk, yk) is contained in the test response (E).
摘要翻译：用于测试数字化测试响应的测试装置具有发生器（2）和信号提取器（3）。发生器（2）使用直接数字合成来产生彼此正交的一组n个数字参考信号（x，k，y，k）。在这种情况下，n是大于1的自然数。信号提取器（3）包含测试输入和多个参考输入。测试输入接收数字化的测试响应（E），并且参考输入连接到由发生器（2）产生的参考信号（x，k，y，k））。信号提取器（3）从相应的参考信号（x k，y k k）和测试响应（E）产生标量积，并且使用所述乘积来计算是否在测试响应（E）中包含参考信号（x，k，y，k）的组合。

4. 发明授权

US07206712B2 Test apparatus and test method for mixed-signal semiconductor components 有权
标题翻译：混合信号半导体元件的测试装置和测试方法
公开(公告)号：US07206712B2
公开(公告)日：2007-04-17
申请号：US11395528
申请日：2006-04-03
申请人： Sebastian Sattler , Heinz Mattes
发明人： Sebastian Sattler , Heinz Mattes
IPC分类号： G01R27/28
CPC分类号： G01R31/3167 , G01R31/31924 , G01R31/31926
摘要： A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The semiconductor component is operated using a test sequence, with the reference signal being applied to the semiconductor component or to the evaluation apparatus.
摘要翻译：通过提供测试器，加载板和评估装置来测试半导体部件。使用测试序列来操作半导体部件，其中参考信号被施加到半导体部件或评估装置。

5. 发明申请

US20060238392A1 Test apparatus and test method for mixed-signal semiconductor components 有权
标题翻译：混合信号半导体元件的测试装置和测试方法
公开(公告)号：US20060238392A1
公开(公告)日：2006-10-26
申请号：US11395528
申请日：2006-04-03
申请人： Sebastian Sattler , Heinz Mattes
发明人： Sebastian Sattler , Heinz Mattes
IPC分类号： H03M1/10
CPC分类号： G01R31/3167 , G01R31/31924 , G01R31/31926
摘要： A semiconductor component is tested by providing a tester, a loadboard and an evaluation apparatus. The loadboard provided with the semiconductor component, and a reference signal is generated according to the following: providing a number n of periods for which signal values are generated, where n is a natural number greater than 1; a number m of samples is provided, where n and m are prime numbers; a step size h is stipulated on the basis of the equation h=n*360°/m; the initial value for the cosine x0 and for the sine y0 is stipulated; the cosine value xi+1 and the sine value yi+1 for the following time (i+1)*h are calculated from the sine value yi and the cosine value xi for the present time i*h, the calculation being performed in an electrical circuit which is situated on the loadboard or in the semiconductor component to be tested; and the previous calculation is repeated in a loop with a control variable i which runs from 0 to m. The semiconductor component is operated using a test sequence, with the reference signal being applied to the semiconductor component or to the evaluation apparatus.
摘要翻译：通过提供测试器，加载板和评估装置来测试半导体部件。设置有半导体元件的装载板和参考信号根据以下产生：提供产生信号值的n个周期，其中n是大于1的自然数; 提供m个样本，其中n和m是素数; 基于等式h = n * 360°/ m规定步长h; 规定余弦x <0>和正弦y <0>的初始值; 对于随后的时间（i + 1）* h的余弦值x i + 1和正弦值y i + 1＆lt; i＆gt;从正弦值y i＆lt; i＆gt;和余弦值x i i i i h h，计算是在位于加载板上或要测试的半导体部件中的电路中执行的; 并且以从0到m的控制变量i的循环重复先前的计算。使用测试序列来操作半导体部件，其中参考信号被施加到半导体部件或评估装置。

6. 发明授权

US07653170B2 Electrical circuit for measuring times and method for measuring times 有权
标题翻译：测量时间的电路和测量时间的方法
公开(公告)号：US07653170B2
公开(公告)日：2010-01-26
申请号：US11440481
申请日：2006-05-25
申请人： Heinz Mattes , Thomas Piorek , Sebastian Sattler , Olaf Stroeble
发明人： Heinz Mattes , Thomas Piorek , Sebastian Sattler , Olaf Stroeble
IPC分类号： G04F10/04
CPC分类号： G01R31/31922 , G01R31/31937 , G04F10/04 , G04F10/06
摘要： An electrical circuit used for measuring times is disclosed. In one embodiment, the electrical circuit has a counter, a decoder and a multiplicity of time trap elements. At least the counter and the time trap elements are located together on an integrated semiconductor component. Each time trap element has a data input, a clock input, a delay output and a output port. The time trap element contains a delay element and a flip flop. The delay element outputs a signal change at the data input with a time delay at the delay output. The flip flop has a data input, a clock input and an output port, the data inputs, the clock inputs and the output ports of the flip flop and of the time trap element being connected to one another. The time trap elements are connected as ring oscillator.
摘要翻译：公开了一种用于测量时间的电路。在一个实施例中，电路具有计数器，解码器和多个时间陷波元件。至少计数器和时间陷阱元件一起位于集成半导体部件上。每次陷阱元件都具有数据输入，时钟输入，延迟输出和输出端口。时间陷阱元件包含延迟元件和触发器。延迟元件在延迟输出端以时间延迟输出数据输入端的信号变化。触发器具有数据输入，时钟输入和输出端口，触发器的数据输入，时钟输入和输出端口以及时间陷阱元件彼此连接。时间陷阱元件连接为环形振荡器。

7. 发明授权

US07400995B2 Device and method for testing integrated circuits 有权
标题翻译：集成电路测试装置和方法
公开(公告)号：US07400995B2
公开(公告)日：2008-07-15
申请号：US10566461
申请日：2004-07-08
申请人： Heinz Mattes , Sebastian Sattler
发明人： Heinz Mattes , Sebastian Sattler
IPC分类号： G06F19/00
CPC分类号： G01R31/2839 , G01R35/005
摘要： A test device and method is disclosed. In one embodiment, the test device includes a precision signal generator for generating a test signal, which generator is connected via a respective connecting line to a respective input contact intended for connection to an input of an integrated circuit, and at least one reference signal generator for generating a reference signal. Furthermore, at least one comparator unit is provided for a respective input contact said comparator unit being able to be operated in a test mode. In the test mode, the test signal is compared with the reference signal. The precision signal generator is turned off by the comparator unit if the test signal exceeds or falls below the reference signal.
摘要翻译：公开了一种测试装置和方法。在一个实施例中，测试装置包括用于产生测试信号的精密信号发生器，该发生器经由相应的连接线连接到用于连接到集成电路的输入的相应输入触点，以及至少一个参考信号发生器用于产生参考信号。此外，为相应的输入触点提供至少一个比较器单元，所述比较器单元能够在测试模式下操作。在测试模式下，将测试信号与参考信号进行比较。如果测试信号超过或低于参考信号，则比较器单元关闭精密信号发生器。

8. 发明申请

US20070226602A1 Measuring device and method for measuring relative phase shifts of digital signals 有权
标题翻译：用于测量数字信号相对相移的测量装置和方法
公开(公告)号：US20070226602A1
公开(公告)日：2007-09-27
申请号：US11530257
申请日：2006-09-08
申请人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
发明人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
IPC分类号： G06F11/00
CPC分类号： G01R31/31711 , G01R25/00 , G01R31/31725
摘要： M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0≦n ≦N−1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tφ is calculated by ∑ i = 0 M - 1 ⁢ ⁢ Idx ⁡ ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.
摘要翻译：接收测试信号和参考信号的M个周期。在每种情况下，测试信号和参考信号的周期都是长的。测试信号以采样频率f N 1 = 1 / T S N的采样值采样。此外，N * T S = M * T S，其中N> M。采样值逐渐被n编号，0 <= n <= N-1。采样值相对于参考信号具有限定的相对相移。相位偏移T 由 $< MUNDEROVER> Σi=0MI> -1>Idx（iMO>+K，K为常数，Idx（i）对应于在参考信号的第i个时段期间的测试信号过零之后的第一采样值或最后采样值的数量n 在参考信号的第i个周期之前的测试信号过零之前。只考虑上升或下降的零交叉点。$

9. 发明授权

US07945406B2 Measuring device and method for measuring relative phase shifts of digital signals 有权
标题翻译：用于测量数字信号相对相移的测量装置和方法
公开(公告)号：US07945406B2
公开(公告)日：2011-05-17
申请号：US11530257
申请日：2006-09-08
申请人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
发明人： Stephane Kirmser , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R25/00 , G01R29/26
CPC分类号： G01R31/31711 , G01R25/00 , G01R31/31725
摘要： M periods of the test signal and of the reference signal are received. The periods of the test signal and of the reference signal are in each case Tsig long. The test signal is sampled with N sampled values at a sampling frequency fs=1/Ts. Also, N*Ts=M*Tsig, where N>M. The sampled values are numbered progressively by n, for which 0≦n ≦N−1. The sampled values have a defined relative phase shift with respect to the reference signal. The phase shift Tφ is calculated by ∑ i = 0 M - 1 ⁢ ⁢ Idx ⁡ ( i ) + K , K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising or only falling zero crossings are taken into account.
摘要翻译：接收测试信号和参考信号的M个周期。测试信号和参考信号的周期在每种情况下都是长度。以采样频率fs = 1 / Ts的N个采样值对测试信号进行采样。另外，N * Ts = M * Tsig，其中N> M。采样值逐渐被n编号，其中0＆nlE; n＆nlE; N-1。采样值相对于参考信号具有限定的相对相移。相移T＆phgr 通过Σi = 0 M -1优先Idx⁡（i）+ K，K是常数，Idx（i）对应于在参考期间测试信号过零之后的第一采样值的数量n 在参考信号第i个周期之前，测试信号过零之前的信号第i个周期或最后一个采样值。只考虑上升或下降的零交叉点。

10. 发明授权

US07471220B2 Electronic test circuit for an integrated circuit and methods for testing the driver strength and for testing the input sensitivity of a receiver of the integrated circuit 有权
标题翻译：用于集成电路的电子测试电路和用于测试驱动器强度并用于测试集成电路的接收器的输入灵敏度的方法
公开(公告)号：US07471220B2
公开(公告)日：2008-12-30
申请号：US11622779
申请日：2007-01-12
申请人： Heinz Mattes , Sebastian Sattler
发明人： Heinz Mattes , Sebastian Sattler
IPC分类号： H03M1/10
CPC分类号： G01R31/31716 , G01R31/3167 , G01R31/31917
摘要： The electronic test circuit for an integrated circuit to be tested has an input for receiving an analog data stream (23), a programmable digital line emulator (TPE1) for emulating properties of a transmission path and an output for emitting an analog data stream (24) having a signal-to-noise ratio which can be adjusted using the programmable digital line emulator (TPE1).
摘要翻译：用于要测试的集成电路的电子测试电路具有用于接收模拟数据流（23），用于仿真传输路径属性的可编程数字线路仿真器（TPE1）和用于发射模拟数据流（24）的输出的输入）具有可以使用可编程数字线路仿真器（TPE1）进行调整的信噪比。

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