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1. 发明授权

US08060800B2 Evaluation circuit and method for detecting and/or locating faulty data words in a data stream Tn 有权
标题翻译：用于检测和/或定位数据流Tn中的故障数据字的评估电路和方法
公开(公告)号：US08060800B2
公开(公告)日：2011-11-15
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流Tn的公共输入线。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

2. 发明申请

US20070168814A1 Device and method for testing and for diagnosing digital circuits 有权
标题翻译：用于测试和诊断数字电路的装置和方法
公开(公告)号：US20070168814A1
公开(公告)日：2007-07-19
申请号：US11364369
申请日：2006-03-01
申请人： Andreas Leininger , Michael Goessel
发明人： Andreas Leininger , Michael Goessel
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/40
摘要： A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.
摘要翻译：测试装置包括测试输入信号发生器，其产生字宽N的测试输入信号，以及连接到要测试的电路的输入和输出的端子。电路包括N个数字测试输入和M个数字测试输出。测试输入的端子连接到测试输入信号，并且驱动电路，使得其测试输出以长度为L的宏时钟周期T作为测试响应输出数据。压实机包括连接到端子的M个输入端，用于待测电路的测试输出。压实机用长度为l的微时钟周期t压缩测试响应，并输出宽度为m的数据字，其中长度L至少是长度l的两倍。

3. 发明授权

US08312332B2 Device and method for testing and for diagnosing digital circuits 有权
标题翻译：用于测试和诊断数字电路的装置和方法
公开(公告)号：US08312332B2
公开(公告)日：2012-11-13
申请号：US11364369
申请日：2006-03-01
申请人： Andreas Leininger , Michael Goessel
发明人： Andreas Leininger , Michael Goessel
IPC分类号： G01R31/28
CPC分类号： G01R31/31928 , G01R31/31922 , G01R31/31937 , G11C29/40
摘要： A test apparatus includes a test input signal generator that generates a test input signal of word width N, and terminals that connect to inputs and outputs of an electrical circuit to be tested. The electrical circuit includes N digital test inputs and M digital test outputs. The terminals for the test inputs are connected to the test input signal and an electrical circuit is driven such that it outputs at its test outputs data with a macro clock cycle T of length L as test response. A compactor includes M inputs that are connected to the terminals for the test outputs of the circuit to be tested. The compactor compacts the test response with a micro clock cycle t of length l and outputs a data word of width m, where the length L is at least twice as large as the length l.
摘要翻译：测试装置包括测试输入信号发生器，其产生字宽N的测试输入信号，以及连接到要测试的电路的输入和输出的端子。电路包括N个数字测试输入和M个数字测试输出。测试输入的端子连接到测试输入信号，并且驱动电路，使得其测试输出以长度为L的宏时钟周期T作为测试响应输出数据。压实机包括连接到端子的M个输入端，用于待测电路的测试输出。压实机用长度为l的微时钟周期t压缩测试响应，并输出宽度为m的数据字，其中长度L至少是长度l的两倍。

4. 发明申请

US20080263421A1 Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit 有权
标题翻译：电气诊断电路和集成电路测试和/或诊断分析方法
公开(公告)号：US20080263421A1
公开(公告)日：2008-10-23
申请号：US10568842
申请日：2004-08-11
申请人： Michael Goessel , Andreas Leininger
发明人： Michael Goessel , Andreas Leininger
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.
摘要翻译：公开了电诊断电路和测试方法。在一个实施例中，用于测试集成电路的电诊断电路包括多个外部输入，多个基本相似的串联连接的开关单元和电路输出。开关单元被构造为可控制的，使得根据开关单元的控制信号存在于开关单元的内部输入端的输入信号可以被不变地转发到开关单元的内部输入端在每种情况下布置在下游，或者可以在外部输入处存在的每种情况下与测试信号组合。

5. 发明申请

US20080040638A1 Evaluation Circuit and Method for Detecting and/or Locating Faulty Data Words in a Data Stream Tn 有权
标题翻译：用于检测和/或定位数据流中的故障数据字的评估电路和方法
公开(公告)号：US20080040638A1
公开(公告)日：2008-02-14
申请号：US10577288
申请日：2004-10-22
申请人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
发明人： Michael Goessel , Andreas Leininger , Heinz Mattes , Sebastian Sattler
IPC分类号： G06F11/22
CPC分类号： G01R31/31932 , G01R31/31703
摘要： An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.
摘要翻译：公开了一种用于检测数据流中的错误数据字的评估电路和方法。在一个实施例中，根据本发明的评估电路包括并联连接的第一线性自动机电路和第二线性自动机电路，每个具有一组状态z，其具有用于接收数据流T n 。第一线性自动机电路和第二线性自动机电路被设计成可以分别计算第一签名和第二签名。位于两个线性自动机电路的下游分别是第一逻辑组合门和第二逻辑组合门，其将由线性自动机电路分别计算的签名与可预定的良好签名进行比较并输出比较值。

6. 发明授权

US07814384B2 Electrical diagnostic circuit and method for the testing and/or the diagnostic analysis of an integrated circuit 有权
标题翻译：用于集成电路的测试和/或诊断分析的电气诊断电路和方法
公开(公告)号：US07814384B2
公开(公告)日：2010-10-12
申请号：US10568842
申请日：2004-08-11
申请人： Michael Goessel , Andreas Leininger
发明人： Michael Goessel , Andreas Leininger
IPC分类号： G01R31/28 , G01R31/26 , G11C29/00 , G06F17/50
CPC分类号： G01R31/318547
摘要： An electrical diagnostic circuit and testing method is disclosed. In one embodiment, the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input.
摘要翻译：公开了电诊断电路和测试方法。在一个实施例中，用于测试集成电路的电诊断电路包括多个外部输入，多个基本相似的串联连接的开关单元和电路输出。开关单元被构造为可控制的，使得根据开关单元的控制信号存在于开关单元的内部输入端的输入信号可以被不变地转发到开关单元的内部输入端在每种情况下布置在下游，或者可以在外部输入处存在的每种情况下与测试信号组合。

7. 发明授权

US08539321B2 Apparatus and method for correcting at least one bit error within a coded bit sequence 有权
标题翻译：用于校正编码比特序列内的至少一个比特差错的装置和方法
公开(公告)号：US08539321B2
公开(公告)日：2013-09-17
申请号：US12943520
申请日：2010-11-10
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stéphane Lacouture
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt , Stéphane Lacouture
IPC分类号： H04M13/00
CPC分类号： H03M13/151 , H03M13/152 , H03M13/155 , H03M13/1575 , H03M13/159 , H03M13/616 , H03M13/6575
摘要： An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
摘要翻译：用于校正编码比特序列中的至少一个比特误差的装置包括误差校正子发生器和比特误差校正器。错误校正子发生器确定通过校验矩阵与编码比特序列的乘法导出的编码比特序列的错误校正。

8. 发明申请

US20130173979A1 HIGH PERFORMANCE COMPACTION FOR TEST RESPONSES WITH MANY UNKNOWNS 有权
标题翻译：高性能压力测试响应与多个知识
公开(公告)号：US20130173979A1
公开(公告)日：2013-07-04
申请号：US13643107
申请日：2011-05-18
申请人： Michael Goessel , Michael Richter , Thomas Rabenalt
发明人： Michael Goessel , Michael Richter , Thomas Rabenalt
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318563 , G01R31/318583
摘要： A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m
摘要翻译：一种电路装置，用于利用具有N个扫描路径的电子电路的X值来控制对测试和诊断数据的掩蔽，其中测试数据在由具有m个输入和N个输出的解压缩器插入到N个扫描路径中时提供（m

9. 发明申请

US20120144260A1 Apparatus and Method for Detecting an Error Within a Coded Binary Word 有权
标题翻译：用于检测编码二进制字中的错误的装置和方法
公开(公告)号：US20120144260A1
公开(公告)日：2012-06-07
申请号：US12959838
申请日：2010-12-03
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： G06F11/10
CPC分类号： H03M13/3776 , H03M13/13 , H03M13/19 , H03M13/3738
摘要： An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.
摘要翻译：用于检测编码二进制字中的误差的装置包括误差校正器和误差检测器。误差校正器校正由错误校正码编码的故障编码二进制字的位的有故障子集内的可校正位错误，使得校正的位子集等于纠错码字的相应子集代码，如果错误校正器工作无效。此外，误差检测器确定指示误差检测器输入二进制字是否是纠错码的码字的错误检测比特序列。误差检测器输入二进制字基于包含校正的比特子集的校正的编码二进制字，并且最大限度地存在故障编码的二进制字的位的适当子集。

10. 发明授权

US07870473B2 Error detection device for an address decoder, and device for error detection for an address decoder 有权
标题翻译：用于地址解码器的错误检测装置，以及用于地址解码器的错误检测装置
公开(公告)号：US07870473B2
公开(公告)日：2011-01-11
申请号：US11672638
申请日：2007-02-08
申请人： Michael Goessel , Franz Klug , Jorge Guajardo Merchan , Steffen Marc Sonnekalb
发明人： Michael Goessel , Franz Klug , Jorge Guajardo Merchan , Steffen Marc Sonnekalb
IPC分类号： G06F7/02 , H03M13/00
CPC分类号： G06F11/1016
摘要： An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the 1-out-of-n decoder, and a comparer for receiving the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.
摘要翻译：一种用于地址解码器的错误检测装置，其使用1-out-n解码器将多个有效输出地址中的输入地址转换为相关联的输出地址，所述错误检测装置包括：再生器，用于在基于1输出解码器的输出地址的基础，以及用于接收输入地址和再生地址并根据输入地址和再生地址的比较输出信号的比较器，其中如果输入地址和再生地址不匹配，则表示输入地址转换为输出地址的错误，如果输入地址等于重新生成的地址，则表示输入地址无误转换为输出地址。

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