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1. 发明授权

US10025343B2 Data transfer between asynchronous clock domains 有权
公开(公告)号：US10025343B2
公开(公告)日：2018-07-17
申请号：US13991602
申请日：2011-12-28
申请人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
发明人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
IPC分类号： G06F1/12 , G06F13/42
摘要： Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

2. 发明申请

US20130254583A1 DATA TRANSFER BETWEEN ASYNCHRONOUS CLOCK DOMAINS 有权
标题翻译：非同步时钟域之间的数据传输
公开(公告)号：US20130254583A1
公开(公告)日：2013-09-26
申请号：US13991602
申请日：2011-12-28
申请人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
发明人： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F13/4291
摘要： Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.
摘要翻译：本文公开的一些实施例提供了用于在异步时钟域之间传送数据的技术和布置。可以由第一时钟域产生同步信号，并且响应于同步信号可以在域之间传送数据。可以与同步信号相比较来监视第二时钟域的时钟周期，以报告每次出现同步信号时出现的第二时钟域周期数。该信息可以通过测试和验证设备来记录，以便于错误分析。

3. 发明授权

US07321963B2 System and method for storing immediate data 失效
公开(公告)号：US07321963B2
公开(公告)日：2008-01-22
申请号：US10773848
申请日：2004-02-05
申请人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
发明人： Alan B. Kyker , Per Hammarlund , Chan Lee , Robert F. Krick , Hitesh Ahuja , William Alexander , Joseph Rohlman
IPC分类号： G06F9/318 , G06F9/28
CPC分类号： G06F9/30178 , G06F9/30156 , G06F9/3016 , G06F9/30167
摘要： An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

4. 发明授权

US06493821B1 Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table 失效
标题翻译：使用指令序列号索引状态信息表从回写阶段事件信号或微分支错误预测中恢复
公开(公告)号：US06493821B1
公开(公告)日：2002-12-10
申请号：US09094027
申请日：1998-06-09
申请人： Reynold V. D'Sa , Robert F. Krick , Rebecca E. Hebda , Alan B. Kyker
发明人： Reynold V. D'Sa , Robert F. Krick , Rebecca E. Hebda , Alan B. Kyker
IPC分类号： G06F938
CPC分类号： G06F9/30174 , G06F9/3863
摘要： A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.
摘要翻译：提供流水线微处理器。流水线微处理器包括回写阶段，其向事件发信号并发送具有该事件的指令的序列号。事件可能是例如故障，陷阱或分支错误预测。流水线微处理器还包括解码级，其存储相应指令的恢复状态信息，并且响应于写回级，通过使用序列号来访问存储的信息以检索具有该事件的指令的恢复状态信息来发信号通知该事件。恢复状态信息可以包括例如指向下一个线性指令的指针，指向分支目标指令的指针，分支预测或指令源。事件恢复微码确定使用恢复状态信息执行的下一条指令，下一条指令在机器恢复后执行。

5. 发明授权

US07334115B1 Detection, recovery and prevention of bogus branches 失效
标题翻译：检测，恢复和预防假枝
公开(公告)号：US07334115B1
公开(公告)日：2008-02-19
申请号：US09608512
申请日：2000-06-30
申请人： Reynold V. D'Sa , Alan B. Kyker , Slade A. Morgan , Rebecca E. Hebda , Richard A. Weier , Robert F. Krick
发明人： Reynold V. D'Sa , Alan B. Kyker , Slade A. Morgan , Rebecca E. Hebda , Richard A. Weier , Robert F. Krick
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3808 , G06F9/3861
摘要： The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.
摘要翻译：本发明提供了一种用于检测和预防微处理器中的虚假分支预测和恢复的方法和装置。从宏指令解码的微操作被存储在解码的微操作高速缓存中。分支预测逻辑确定分支是否为假。如果所采取的分支被确定为假的，则本发明使得从原始虚假分支微操作指令下降的微操作被标记并随后移动到处理器的后端退休。此外，分支预测逻辑（分支预测逻辑存储缓冲器）被更新为分支的实际方向是什么。以这种方式，则检测到虚假的分支，从中进一步预防和恢复。

6. 发明授权

US06865740B2 Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor 有权
标题翻译：将流标记插入到指令流中以指示多线程处理器内的线程切换操作的方法和系统
公开(公告)号：US06865740B2
公开(公告)日：2005-03-08
申请号：US10248000
申请日：2002-09-20
申请人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
发明人： Stavros Kalafatis , Alan B. Kyker , Robert D. Fisch
IPC分类号： G06F9/38 , G06F9/48 , G06F9/00
CPC分类号： G06F9/3802 , G06F9/3808 , G06F9/3844 , G06F9/3851
摘要： A method of performing a thread switching operation within a multithreaded processor includes detecting the dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information of the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. A flow marker is inserted into an instruction stream, the instruction stream including the instruction information of the first thread dispatched from the instruction information source, and the flow marker indicating that the thread switching operation has occurred. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced.
摘要翻译：一种在多线程处理器内执行线程切换操作的方法包括检测第一线程的第一预定量指令信息从指令流缓冲器到多线程处理器内的指令预解码器的调度。响应于检测第一线程的第一预定量指令信息的调度，针对指令流缓冲器的输出执行线程切换操作。流标记被插入到指令流中，指令流包括从指令信息源调度的第一线程的指令信息和指示线程切换操作已经发生的流标记。因此开始从指令流缓存器发送第二线程的指令信息。

7. 发明授权

US06502177B1 Single cycle linear address calculation for relative branch addressing 失效
标题翻译：相对分支寻址的单周期线性地址计算
公开(公告)号：US06502177B1
公开(公告)日：2002-12-31
申请号：US09454076
申请日：1999-12-02
申请人： Jonathan P. Douglas , Alan B. Kyker
发明人： Jonathan P. Douglas , Alan B. Kyker
IPC分类号： G06F1206
CPC分类号： G06F9/342 , G06F9/30167 , G06F9/324 , G06F9/3804
摘要： A method and circuit for linear space target address generation for a relative branch is described. A selection signal is generated to be used in generating a linear space target address. The generation of the linear space target address includes generating multiple corrected target addresses and selecting the linear space target address from the multiple corrected target addresses using the selection signal. The process of generating multiple corrected target addresses includes generating first, second, and third corrected target addresses. The first corrected target address is generated using an address and a displacement. The second corrected target address is generated using the address, displacement, and a second adder correction value. The third corrected target address is generated using the address, displacement, and a third adder correction value. A multiplexer outputs the first, second, or third corrected target address using the selection signal. The selection signal is generated in selection logic using a segment wrap indication and a displacement sign, where the segment wrap indication is generated based on a displacement least significant bits, a segment base, and a least significant address.
摘要翻译：描述了用于相对分支的线性空间目标地址生成的方法和电路。生成选择信号以用于生成线性空间目标地址。线性空间目标地址的生成包括使用选择信号从多个校正目标地址生成多个校正目标地址并选择线性空间目标地址。产生多个经修正的目标地址的过程包括产生第一，第二和第三校正目标地址。使用地址和位移生成第一个修正的目标地址。使用地址，位移和第二加法器校正值来生成第二校正目标地址。使用地址，位移和第三加法器校正值生成第三校正目标地址。复用器使用选择信号输出第一，第二或第三校正目标地址。选择信号在选择逻辑中使用段包裹指示和位移符号来生成，其中基于位移最低有效位，段基和最低有效地址生成段包指示。

8. 发明授权

US06467027B1 Method and system for an INUSE field resource management scheme 有权
标题翻译：用于INUSE现场资源管理方案的方法和系统
公开(公告)号：US06467027B1
公开(公告)日：2002-10-15
申请号：US09475746
申请日：1999-12-30
申请人： Alan B. Kyker , Darrell D. Boggs
发明人： Alan B. Kyker , Darrell D. Boggs
IPC分类号： G06F1200
CPC分类号： G06F9/3812 , G06F12/0875
摘要： A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.
摘要翻译：一种用于使用使用字段来维护在流水线处理器中的指令的方法。该方法包括接收对指令的读取请求，响应于读取请求发送指令并设置与该指令相关联的使用字段以使用。该方法的替代实施例涉及响应于读请求发送指令，接收指令退出通知并重置ITLB中的使用字段。该方法也可以用在ICACHE中，其中使用字段与存储在ICACHE中的每个指令相关联。该方法的其他实施例可以在ITLB和ICACHE中同时使用作为资源跟踪机制来维护资源。

9. 发明授权

US06374350B1 System and method of maintaining and utilizing multiple return stack buffers 失效
标题翻译：维护和利用多个返回堆栈缓冲区的系统和方法
公开(公告)号：US06374350B1
公开(公告)日：2002-04-16
申请号：US09584890
申请日：2000-06-01
申请人： Reynold V. D'Sa , Rebecca E. Hebda , Stavros Kalafatis , Alan B. Kyker , Robert B. Chaput
发明人： Reynold V. D'Sa , Rebecca E. Hebda , Stavros Kalafatis , Alan B. Kyker , Robert B. Chaput
IPC分类号： G06F942
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
摘要翻译：提供微处理器中的指令流水线。指令流水线包括多个流水线单元，多个流水线单元中的每一个处理多个指令。多个流水线单元中的至少两个是流水线的至少一些指令的源。该流水线还包括至少两个推测返回地址堆栈，每个耦合的推测返回地址栈耦合到至少一个指令源单元。每个推测返回地址堆栈都能够存储至少两个推测返回地址。

10. 发明授权

US6151671A System and method of maintaining and utilizing multiple return stack buffers 失效
公开(公告)号：US6151671A
公开(公告)日：2000-11-21
申请号：US27407
申请日：1998-02-20
申请人： Reynold V. D'Sa , Rebecca E. Hebda , Stavros Kalafatis , Alan B. Kyker , Robert B. Chaput
发明人： Reynold V. D'Sa , Rebecca E. Hebda , Stavros Kalafatis , Alan B. Kyker , Robert B. Chaput
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

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