会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明授权
    • Method and system for bypassing a fill buffer located along a first instruction path
    • 绕过位于第一条指令路径的填充缓冲区的方法和系统
    • US06442674B1
    • 2002-08-27
    • US09223297
    • 1998-12-30
    • Chan LeeHitesh AhujaRobert F. Krick
    • Chan LeeHitesh AhujaRobert F. Krick
    • G06F9315
    • G06F9/3814G06F9/3802G06F9/3808
    • A method and system for reducing a latency of microprocessor instructions in transit along an instruction pipeline of a microprocessor by bypassing, at certain times, a fill buffer located between an instruction source and a trace cache unit on the instruction pipeline. The signal path through the fill buffer to the trace cache unit represent a first signal path. In the instruction pipeline, a second signal path is also provided, one which also leads instructions to the trace cache unit, not through the fill buffer, but through a latch provided on the second instruction path. If the latch is enabled, a set of instructions appearing at the input of the fill buffer is transmitted through the latch along the second instruction path and to the trace cache. As a result, the fill buffer is bypassed and a reduced latency for the bypassed instructions is achieved along the instruction pipeline.
    • 一种方法和系统,用于通过在特定时间绕过位于指令流水线上的指令源和跟踪高速缓存单元之间的填充缓冲器来减少沿着微处理器的指令流水线传送的微处理器指令的等待时间。 通过填充缓冲器到跟踪缓存单元的信号路径表示第一信号路径。 在指令流水线中,还提供第二信号路径,其中一个信号路径也不通过填充缓冲器,而是经由设置在第二指令路径上的锁存器将指令引导到跟踪高速缓存单元。 如果锁存器被使能,则出现在填充缓冲器的输入端的一组指令沿着第二指令路径通过锁存器传送到跟踪缓存。 结果,溢出缓冲器被旁路,并且沿着指令流水线实现了绕过指令的降低的等待时间。
    • 9. 发明授权
    • Processor instruction pipeline with error detection scheme
    • 具有错误检测方案的处理器指令流水线
    • US06457119B1
    • 2002-09-24
    • US09360192
    • 1999-07-23
    • Darrell BoggsRobert F. KrickChan Lee
    • Darrell BoggsRobert F. KrickChan Lee
    • G06F938
    • G06F9/3865G06F9/3842G06F11/0721G06F11/0793G06F11/1405
    • Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.
    • 简而言之,根据本发明的一个实施例,处理器包括:多单元指令流水线。 指令流水线包括微码源。 微代码源包括检测至少一个损坏的微代码指令的发生的能力。 微代码源还能够向至少一个其他指令流水线单元发出至少一个损坏的微代码指令的发生。 简而言之,根据本发明的另一个实施例,执行微码指令的方法包括以下。 检测到存在至少一个损坏的微代码指令,并发出至少一个损坏的微代码指令的发生。 简而言之,根据本发明的另一实施例,一种系统包括:具有微码源的处理器,其能够检测至少一个损坏的微代码指令的发生,并向至少一个其他信号发送至少一个损坏的微代码指令的发生 指令流水线单元。 采用处理器的系统还包括主存储器,视频卡,系统总线和批量存储能力。