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1. 发明授权

US07920701B1 System and method for digital content protection 有权
标题翻译：数字内容保护的系统和方法
公开(公告)号：US07920701B1
公开(公告)日：2011-04-05
申请号：US11304408
申请日：2005-12-14
申请人： Michael Brian Cox , Henry Packard Moreton , Brian Keith Langendorf , David G. Reed
发明人： Michael Brian Cox , Henry Packard Moreton , Brian Keith Langendorf , David G. Reed
IPC分类号： H04N7/167
CPC分类号： H04N21/4367 , H04N21/42646 , H04N21/4325 , H04N21/4405 , H04N21/4408
摘要： A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.
摘要翻译：公开了数字内容系统。布置在桥中的安全引擎提供加密服务。从中央处理单元接收到的清除文本数字数据被加密并通过不安全数据路径作为密文通过桥传输。

2. 发明授权

US08473750B2 Chipset security offload engine 有权
标题翻译：芯片组安全卸载引擎
公开(公告)号：US08473750B2
公开(公告)日：2013-06-25
申请号：US11304116
申请日：2005-12-14
申请人： Michael Brian Cox , Henry Packard Moreton , Brian Keith Langendorf , David G. Reed
发明人： Michael Brian Cox , Henry Packard Moreton , Brian Keith Langendorf , David G. Reed
IPC分类号： G06F11/30 , G06F12/14 , G06F7/04 , G06F17/30 , H04N7/167 , H04N7/16
CPC分类号： H04N21/4367 , G06F21/72 , H04N5/775 , H04N5/85 , H04N5/913 , H04N7/1675 , H04N21/4113 , H04N21/4122 , H04N21/42646 , H04N21/4325 , H04N2005/91364
摘要： A bridge is disclosed having a security engine to protect digital content at insecure interfaces of the bridge. The bridge permits cryptographic services to he offloaded from a central processing unit to the bridge. The bridge receives a clear text input from a central processing unit. The bridge encrypts the clear text input as cipher text for storage in a memory. The bridge provided the cipher text to a graphics processing unit.
摘要翻译：公开了一种具有安全引擎以在桥的不安全接口处保护数字内容的桥。该桥允许从中央处理单元卸载到桥上的加密服务。桥接器从中央处理单元接收明文输入。桥将加密明文输入作为密文用于存储在内存中。桥将密文提供给图形处理单元。

3. 发明授权

US07650645B1 Trusted bus transactions 有权
标题翻译：可信总线交易
公开(公告)号：US07650645B1
公开(公告)日：2010-01-19
申请号：US11133956
申请日：2005-05-20
申请人： Brian Keith Langendorf , Michael Brian Cox
发明人： Brian Keith Langendorf , Michael Brian Cox
IPC分类号： G06F1/26 , G06F21/00 , G06F7/04
CPC分类号： G06F21/606
摘要： Circuits, methods, and apparatus that provide for trusted transactions between a device and system memory. In one exemplary embodiment of the present invention, a host processor asserts and de-asserts trust over a virtual wire. The device accesses certain data if the host processor provides a trusted instruction for it to do so. Once the device attempts to access this certain data, or perform a certain type of data access, a memory controller allows the access on the condition that the host processor previously made the trusted instruction. The device then accepts data if trust is asserted during the data transfer.
摘要翻译：提供设备和系统存储器之间信任事务的电路，方法和设备。在本发明的一个示例性实施例中，主机处理器通过虚拟线路断言和取消断言信任。如果主机处理器为其提供可信指令，则设备访问某些数据。一旦设备尝试访问该特定数据或执行某种类型的数据访问，存储器控制器允许在主处理器先前做出可信指令的条件下进行访问。然后，如果在数据传输过程中信任被断言，则设备接受数据。

4. 发明授权

US08234458B2 System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message 有权
标题翻译：使用窥探请求和完整消息在串行接口总线上维护高速缓存一致性的系统和方法
公开(公告)号：US08234458B2
公开(公告)日：2012-07-31
申请号：US12331302
申请日：2008-12-09
申请人： Brian Keith Langendorf , David B. Glasco , Michael Brian Cox , Jonah M. Alben
发明人： Brian Keith Langendorf , David B. Glasco , Michael Brian Cox , Jonah M. Alben
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F12/0831
摘要： A method and system for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The method includes generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus, and causing the snoop request to be transmitted over the serial interface bus to a second processor. The method further includes extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.
摘要翻译：一种用于在串行接口总线（例如外围组件互连Express（PCIe）总线）上维持高速缓存一致性的方法和系统。该方法包括产生窥探请求（SNP）以确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓冲存储器中的第二数据是相干的，该侦听请求包括识别串行接口总线上的数据高速缓存的目的地信息，以及导致窥探请求通过串行接口总线传输到第二处理器。该方法还包括从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成指示第一数据与第二数据相干的完整消息（CPL），以及使完整消息传输总线到第一个处理器。窥探请求和完成消息可以是供应商定义的消息。

5. 发明申请

US20100146218A1 System And Method For Maintaining Cache Coherency Across A Serial Interface Bus 有权
标题翻译：通过串行接口总线维护缓存一致性的系统和方法
公开(公告)号：US20100146218A1
公开(公告)日：2010-06-10
申请号：US12331302
申请日：2008-12-09
申请人： Brian Keith Langendorf , David B. Glasco , Michael Brian Cox , Jonah M. Alben
发明人： Brian Keith Langendorf , David B. Glasco , Michael Brian Cox , Jonah M. Alben
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method for executing processing operations using data stored in a memory. The method includes generating a snoop request configured to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on a bus, and a cache line address identifying where in the data cache the second data is located. The method further includes causing the snoop request to be transmitted over the bus to the second processor, extracting the cache line address from the snoop request, determining whether the second data is coherent, generating a complete message that includes completion information indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor.
摘要翻译：一种使用存储在存储器中的数据执行处理操作的方法。该方法包括：生成窥探请求，被配置为确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓存中的第二数据是相干的，该窥探请求包括标识总线上的数据高速缓存的目的地信息和高速缓存行地址识别第二数据位于数据高速缓存中的位置。该方法还包括使窥探请求通过总线传送到第二处理器，从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成完整消息，其中包括指示第一数据的完成信息与第二数据一致，并且使整个消息通过总线传送到第一处理器。

6. 发明授权

US08782349B2 System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message 有权
标题翻译：使用窥探请求和完整消息在串行接口总线上维护高速缓存一致性的系统和方法
公开(公告)号：US08782349B2
公开(公告)日：2014-07-15
申请号：US13557980
申请日：2012-07-25
申请人： Brian Keith Langendorf , David B. Glasco , Michael Brian Cox , Jonah M. Alben
发明人： Brian Keith Langendorf , David B. Glasco , Michael Brian Cox , Jonah M. Alben
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.
摘要翻译：公开了用于通过串行接口总线（例如外围组件互连Express（PCIe）总线）来维持高速缓存一致性的技术。这些技术包括产生窥探请求（SNP）以确定存储在本地存储器中的第一数据是否相对于存储在数据高速缓存中的第二数据是相干的，该窥探请求包括识别串行接口总线上的数据高速缓存的目的地信息，并导致通过串行接口总线传送到第二处理器的窥探请求。所述技术还包括从窥探请求中提取高速缓存线地址，确定第二数据是否相干，生成指示第一数据与第二数据相干的完整消息（CPL），并且使得完整的消息被传送总线到第一个处理器。窥探请求和完成消息可以是供应商定义的消息。

7. 发明授权

US07053901B2 System and method for accelerating a special purpose processor 有权
标题翻译：用于加速专用处理器的系统和方法
公开(公告)号：US07053901B2
公开(公告)日：2006-05-30
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
发明人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译：本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU，或者管理专用处理器的驱动器。有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。可以基于性能考虑，有选择地使用协处理器。

8. 发明授权

US07289125B2 Graphics device clustering with PCI-express 有权
标题翻译：使用PCI-express的图形设备集群
公开(公告)号：US07289125B2
公开(公告)日：2007-10-30
申请号：US10789248
申请日：2004-02-27
申请人： Franck R. Diard , David G. Reed , Gary D. Hicok , Michael Brian Cox
发明人： Franck R. Diard , David G. Reed , Gary D. Hicok , Michael Brian Cox
IPC分类号： G06F15/00 , G06F15/16
CPC分类号： G06F3/14 , G06F3/1438 , G06T1/20 , G06T15/005 , G09G5/363
摘要： A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.
摘要翻译：与广播孔径相关联的桥接器有助于在处理器和多个图形设备之间传送渲染命令和数据。桥接器将处理器写入的数据接收到广播孔径并将其转发到多个图形设备，从而无需处理器执行重复（？）写入操作。在系统初始化期间，基于使用系统配置实用程序设置的存储在系统配置存储器中的孔径大小值，将广播孔径分配给地址空间中的桥。图形驱动器通过经由桥驱动器将与多个图形设备相关联的单播孔径参数发送到桥接器来激活广播孔径。在激活广播孔径时，可以并行地操作多个图形设备以提高渲染性能。并行渲染技术包括分割帧，备用帧以及组合分割和交替帧渲染。

9. 发明授权

US09158896B2 Method and system for generating a secure key 有权
标题翻译：用于生成安全密钥的方法和系统
公开(公告)号：US09158896B2
公开(公告)日：2015-10-13
申请号：US12029432
申请日：2008-02-11
申请人： Michael Brian Cox , Phillip Norman Smith , Stephen Donald Lew
发明人： Michael Brian Cox , Phillip Norman Smith , Stephen Donald Lew
IPC分类号： H04L9/00 , G06F21/10 , G06F21/57 , G06F21/72 , H04L9/08
CPC分类号： G06F21/10 , G06F21/575 , G06F21/72 , G06F2221/0755 , H04L9/0822 , H04L9/0866 , H04L2209/20 , H04L2209/603
摘要： A method, system on a chip, and computer system for generating more robust keys which utilize data occupying relatively small die areas is disclosed. Embodiments provide a convenient and effective mechanism for generating a key for use in securing data on a portable electronic device, where the key is generated from repurposed data and a relatively small amount. A multi-stage encryption algorithm may be performed to generate the key, where the first stage may include encrypting the secure data, and the second stage may include encrypting the result of a logical operation on the encrypted secure data with a unique identifier of the portable electronic device. A secret key may be used as the encryption key for each stage. The result of the second encryption stage may include the generated key which may be used to perform subsequent operations on the portable electronic device.
摘要翻译：公开了一种用于生成利用占据相对较小管芯区域的数据的更健壮的密钥的方法，芯片上的系统和计算机系统。实施例提供了一种用于生成用于保护便携式电子设备上的数据的密钥的方便和有效的机制，其中密钥是由重新利用的数据产生的，并且数量相对较少。可以执行多级加密算法来生成密钥，其中第一级可以包括对安全数据进行加密，并且第二级可以包括用加密的安全数据的加密安全数据的唯一标识符加密逻辑操作的结果电子设备。秘密密钥可以用作每个阶段的加密密钥。第二加密阶段的结果可以包括可用于在便携式电子设备上执行后续操作的所生成的密钥。

10. 发明授权

US08645634B1 Zero-copy data sharing by cooperating asymmetric coprocessors 有权
标题翻译：通过合作的非对称协处理器进行零拷贝数据共享
公开(公告)号：US08645634B1
公开(公告)日：2014-02-04
申请号：US12355648
申请日：2009-01-16
申请人： Michael Brian Cox , Nicholas Patrick Wilt , Richard Hough
发明人： Michael Brian Cox , Nicholas Patrick Wilt , Richard Hough
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/28
摘要： One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.
摘要翻译：本发明的一个实施例提出了一种用于减少分配给主处理器和协处理器的存储器之间的数据复制的技术。系统存储器被别名为设备存储器，以允许协处理器和主处理器共享存储器的相同部分。任一设备可以写入和/或读取存储器的共享部分以在设备之间传送数据，而不是将数据从只能由一个设备访问的存储器的一部分复制到只能由另一个设备访问的存储器的不同部分。清除对处理器内存和协处理器存储器到主处理器存储器副本的明确的主处理器存储器的需要改进了应用的性能，并减少了应用的物理存储器要求，因为一部分存储器被共享而不是分配存储器的独立私有部分。

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