专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07053901B2 System and method for accelerating a special purpose processor 有权
标题翻译：用于加速专用处理器的系统和方法
公开(公告)号：US07053901B2
公开(公告)日：2006-05-30
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
发明人： Jen-Hsun Huang , Michael Brian Cox , Ziyad S. Hakura , John S. Montrym , Brad W. Simeral , Brian Keith Langendorf , Blanton Scott Kephart , Franck R. Diard
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译：本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU，或者管理专用处理器的驱动器。有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。可以基于性能考虑，有选择地使用协处理器。

2. 发明授权

US5640337A Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC 失效
公开(公告)号：US5640337A
公开(公告)日：1997-06-17
申请号：US696141
申请日：1996-08-13
申请人： Jen-Hsun Huang , Michael D. Rostoker , David Gluss
发明人： Jen-Hsun Huang , Michael D. Rostoker , David Gluss
IPC分类号： G06F11/26 , G06F17/50 , G06F17/00 , G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G06F17/5022
摘要： A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.

3. 发明授权

US5629876A Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC 失效
标题翻译：具有先行ASIC的电子系统的临时现场测试方法和装置
公开(公告)号：US5629876A
公开(公告)日：1997-05-13
申请号：US937643
申请日：1992-08-31
申请人： Jen-Hsun Huang , Michael D. Rostoker , David Gluss
发明人： Jen-Hsun Huang , Michael D. Rostoker , David Gluss
IPC分类号： G06F11/26 , G06F17/50 , G06G7/62
CPC分类号： G06F11/261 , G06F17/5022
摘要： A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.
摘要翻译：描述了一种技术，用于测试目标电子系统的性能，该目标电子系统最终采用包含核心单元和周围逻辑的ASIC，并在临时的基础上使用复杂（设计但尚未制造）的ASIC。在一个实施例中，基本上是核心单元的结合的Q部分或限定部分与被配置为执行周围逻辑的功能的可编程逻辑器件结合使用。 Q部分和可编程逻辑在pod上互连，并插入目标电子系统的临时版本。在另一个实施例中，Q部分被软件模拟并且在盒上互连到可编程逻辑器件。可编程逻辑器件可以在荚果或荚果间进行编程，并且可以监视和控制入口到插入到临时电子系统中的荚的操作的信号。

4. 发明授权

US5477545A Method and apparatus for testing of core-cell based integrated circuits 失效
标题翻译：用于核心电池集成电路测试的方法和装置
公开(公告)号：US5477545A
公开(公告)日：1995-12-19
申请号：US16164
申请日：1993-02-09
申请人： Jen-Hsun Huang
发明人： Jen-Hsun Huang
IPC分类号： G01R31/3185 , G01R31/28 , G06F11/267
CPC分类号： G01R31/318541 , G01R31/318505
摘要： A technique for providing testable core-cell based integrated circuits is described whereby a boundary-scan like technique is employed, but not limited to the external pins (bond pads) of an integrated circuit. An interior boundary-scan path is provided for all peripheral signals of core cells and logic blocks which are not connected to pins of the integrated circuit. This technique provides complete controllability and observability of each core cell and/or logic block on an integrated circuit die, while remaining compatible with test techniques designed into the core cells, and remaining fully compatible with external boundary scan techniques. Method and apparatus are described.
摘要翻译：描述了提供可测试的基于核心单元的集成电路的技术，其中采用边界扫描类似技术，但不限于集成电路的外部引脚（接合焊盘）。为核心单元和逻辑块的所有外围信号提供了内部边界扫描路径，这些信号未连接到集成电路的引脚。该技术提供了集成电路管芯上每个核心单元和/或逻辑块的完全可控性和可观察性，同时与设计到核心单元中的测试技术保持兼容，并且与外部边界扫描技术保持完全兼容。描述了方法和装置。

5. 发明授权

US08253750B1 Digital media processor 有权
标题翻译：数字媒体处理器
公开(公告)号：US08253750B1
公开(公告)日：2012-08-28
申请号：US12832830
申请日：2010-07-08
申请人： Jen-Hsun Huang , Gerrit A. Slavenburg , Stephen D. Lew , John C. Schafer , Thomas F. Fox , Taner E. Ozcelik
发明人： Jen-Hsun Huang , Gerrit A. Slavenburg , Stephen D. Lew , John C. Schafer , Thomas F. Fox , Taner E. Ozcelik
IPC分类号： G06F13/14 , G06F15/80 , G06F15/00
CPC分类号： G06T15/005 , G06F15/78 , G09G5/003 , G09G2360/02 , H04N13/161
摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.
摘要翻译：为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如作为电视机，显示器和网络设备，如打印机和网络录像机。本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

6. 发明申请

US20140055559A1 DIGITAL MEDIA PROCESSOR 审中-公开
标题翻译：数字媒体处理器
公开(公告)号：US20140055559A1
公开(公告)日：2014-02-27
申请号：US13568875
申请日：2012-08-07
申请人： Jen-Hsun Huang , Gerrit A. Slavenburg , Stephen D. Lew , John C. Schafer , Thomas F. Fox , Taner E. Ozcelik
发明人： Jen-Hsun Huang , Gerrit A. Slavenburg , Stephen D. Lew , John C. Schafer , Thomas F. Fox , Taner E. Ozcelik
IPC分类号： G06T15/00 , H04N13/00
CPC分类号： G06T15/005 , G06F15/78 , G09G5/003 , G09G2360/02 , H04N13/161
摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.
摘要翻译：为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如作为电视机，显示器和网络设备，如打印机和网络录像机。本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

7. 发明申请

US20050128203A1 System and method for accelerating a special purpose processor 有权
标题翻译：用于加速专用处理器的系统和方法
公开(公告)号：US20050128203A1
公开(公告)日：2005-06-16
申请号：US10732445
申请日：2003-12-11
申请人： Jen-Hsun Huang , Michael Cox , Ziyad Hakura , John Montrym , Brad Simeral , Brian Langendorf , Blanton Kephart , Franck Diard
发明人： Jen-Hsun Huang , Michael Cox , Ziyad Hakura , John Montrym , Brad Simeral , Brian Langendorf , Blanton Kephart , Franck Diard
IPC分类号： G06T1/00 , G06T1/20 , G06T15/00
CPC分类号： G06T1/20 , G06T15/005
摘要： Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
摘要翻译：本发明的实施例通过使用至少一个协处理器来加速至少一个专用处理器，例如GPU或者管理专用处理器的驱动器。有利地，本发明的实施例是容错的，因为如果使至少一个协处理器变得不可操作，则至少一个GPU或其他专用处理器能够执行所有计算，尽管可能处于较低的性能水平。可以基于性能考虑，有选择地使用协处理器。

8. 发明授权

US06359483B1 Integrated circuit clock distribution system 有权
标题翻译：集成电路时钟分配系统
公开(公告)号：US06359483B1
公开(公告)日：2002-03-19
申请号：US09521811
申请日：2000-03-09
申请人： Daniel Watkins , Jen-Hsun Huang , Ronald Yu
发明人： Daniel Watkins , Jen-Hsun Huang , Ronald Yu
IPC分类号： H03L706
CPC分类号： G06F1/10 , H03L7/0814
摘要： An improved clock distribution system is provided for a multi block network having a series of independent blocks, with each independent block having an average load tap signal. The clock distribution circuit uses the load tap signal from the slowest independent block to synchronize the clock used in the remaining blocks. The clock for the subsequent block is tuned to the average load tap signal of the slowest block. The system clock system is incrementally delayed until it is in tuned with the average load tap signal of the slowest block, then if can be provided to the subsequent blocks of the network. The clock distribution system comprises sequential delay stages to incrementally delay the reference clock signal. The shift register controls each stage of delay, by enabling a multiplexer to allow the incrementally delayed reference clock signal to pass through. Upon reaching a match between a multiplexer output signal and the average load tap signal of the slowest previous block, the shifting stops and the delayed reference clock signal has been synchronized to the average load tap signal of the slowest block.
摘要翻译：为具有一系列独立块的多块网络提供改进的时钟分配系统，每个独立块具有平均负载抽头信号。时钟分配电路使用来自最慢独立块的负载抽头信号来同步其余块中使用的时钟。后续块的时钟调整到最慢块的平均负载抽头信号。系统时钟系统被递增地延迟，直到用最慢块的平均负载分接信号调谐，然后如果可以提供给网络的后续块。时钟分配系统包括顺序延迟级，以递增地延迟参考时钟信号。移位寄存器通过使多路复用器允许递增延迟的参考时钟信号通过来控制延迟的每个阶段。当达到多路复用器输出信号和最慢的前一个块的平均负载抽头信号之间的匹配时，移位停止，延迟的参考时钟信号已经被同步到最慢块的平均负载抽头信号。

9. 发明授权

US5790611A Method and apparatus for adjusting the phase of a digital signal 失效
标题翻译：调整数字信号相位的方法和装置
公开(公告)号：US5790611A
公开(公告)日：1998-08-04
申请号：US289886
申请日：1994-08-12
申请人： Jen-Hsun Huang , Stony Peng
发明人： Jen-Hsun Huang , Stony Peng
IPC分类号： G06F1/10 , H03K5/13 , H03L7/081 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H04L7/0337 , G06F1/10 , H03K5/131 , H03L7/0814
摘要： A method and apparatus for improving the phase granularity when changing the phase of a digital signal. The present invention doubles the phase shift granularity of a phase shifting system by either adding or not adding one-half unit of phase delay to the digital signal being phase shifted. When increasing phase delay is being added to the digital signal, no additional phase delay is added to the digital signal. When decreasing phase delay is being adding to the digital signal, one-half unit of phase delay is added to the digital signal. Thus, whenever a change is made between increasing or decreasing phase delay, a one-half unit phase delay is introduced which effectively doubles the phase delay granularity of the phase delay system at the point of phase delay reversal.
摘要翻译：一种在改变数字信号的相位时改善相位粒度的方法和装置。本发明通过对相移的数字信号增加或不添加一半单位的相位延迟来将相移系统的相移粒度加倍。当增加相位延迟到数字信号时，没有额外的相位延迟被加到数字信号上。当减少相位延迟正在增加数字信号时，将相位延迟的一半单位加到数字信号上。因此，无论何时在相位延迟增加或减小之间进行改变，都会引入半个单位相位延迟，从而在相位延迟反转点有效地将相位延迟系统的相位延迟粒度加倍。

10. 发明授权

US5481209A Clock distribution and control in an integrated circuit 失效
标题翻译：集成电路中的时钟分配和控制
公开(公告)号：US5481209A
公开(公告)日：1996-01-02
申请号：US124093
申请日：1993-09-20
申请人： Raymond H. Lim , Tania Chur , Jen-Hsun Huang
发明人： Raymond H. Lim , Tania Chur , Jen-Hsun Huang
IPC分类号： G06F1/10 , G06F17/50 , H03K19/003 , H03K19/00 , H01L25/00
CPC分类号： G06F17/5077 , G06F1/10 , H03K19/00323
摘要： An apparatus and method for improved clock distribution and control in an integrated circuit which minimizes clock skew between various parts of the integrated circuit chip. Clock loads are evenly distributed between tributaries. Capacitive loading is utilized to balance any differences between tributaries and for minimizing clock skew throughout the integrated circuit.
摘要翻译：一种用于改善集成电路中的时钟分配和控制的装置和方法，其最小化集成电路芯片的各个部分之间的时钟偏移。时钟负载均匀分布在支流之间。电容负载用于平衡支路之间的任何差异，并用于最小化整个集成电路中的时钟偏移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式