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1. 发明申请

US20070300191A1 EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES 有权
标题翻译：非正式金属电厂的有效电磁建模
公开(公告)号：US20070300191A1
公开(公告)日：2007-12-27
申请号：US11849346
申请日：2007-09-03
申请人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
发明人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与相应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

2. 发明申请

US20060282798A1 Efficient electromagnetic modeling of irregular metal planes 失效
标题翻译：不规则金属平面的高效电磁建模
公开(公告)号：US20060282798A1
公开(公告)日：2006-12-14
申请号：US11152580
申请日：2005-06-14
申请人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
发明人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与相应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

3. 发明申请

US20050138584A1 Method, system, and product for verifying voltage drop across an entire integrated circuit package 失效
标题翻译：用于验证整个集成电路封装的电压降的方法，系统和产品
公开(公告)号：US20050138584A1
公开(公告)日：2005-06-23
申请号：US10738708
申请日：2003-12-17
申请人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
发明人： Michael Beattie , Anirudh Devgan , Byron Krauter , Hui Zheng
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036 , G06F2217/40
摘要： A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
摘要翻译：公开了一种用于确定跨整个集成电路封装的电压降的方法，系统和产品。确定整个集成电路封装的几何描述。描述细分为非均匀区域。确定每个不均匀区域的电阻。然后通过组合每个非均匀区域的电阻来确定整个集成电路封装的电阻网表。然后使用网表模拟封装以确定整个集成电路封装的电压降。

4. 发明授权

US07827514B2 Efficient electromagnetic modeling of irregular metal planes 有权
标题翻译：不规则金属平面的高效电磁建模
公开(公告)号：US07827514B2
公开(公告)日：2010-11-02
申请号：US11849346
申请日：2007-09-03
申请人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与对应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

5. 发明申请

US20080052646A1 LITHOGRAPHY AWARE LEAKAGE ANALYSIS 有权
标题翻译： LITHOGRAPHY AWARE泄漏分析
公开(公告)号：US20080052646A1
公开(公告)日：2008-02-28
申请号：US11781043
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068 , G06F2217/12
摘要： A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：执行泄漏分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的泄漏信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

6. 发明授权

US07134103B2 Method, system, and product for verifying voltage drop across an entire integrated circuit package 失效
标题翻译：用于验证整个集成电路封装的电压降的方法，系统和产品
公开(公告)号：US07134103B2
公开(公告)日：2006-11-07
申请号：US10738708
申请日：2003-12-17
申请人： Michael Werner Beattie , Anirudh Devgan , Byron Lee Krauter , Hui Zheng
发明人： Michael Werner Beattie , Anirudh Devgan , Byron Lee Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/40
摘要： A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
摘要翻译：公开了一种用于确定跨整个集成电路封装的电压降的方法，系统和产品。确定整个集成电路封装的几何描述。描述细分为非均匀区域。确定每个不均匀区域的电阻。然后通过组合每个非均匀区域的电阻来确定整个集成电路封装的电阻网表。然后使用网表模拟封装以确定整个集成电路封装的电压降。

7. 发明授权

US08473876B2 Lithography aware timing analysis 有权
标题翻译：光刻感知时序分析
公开(公告)号：US08473876B2
公开(公告)日：2013-06-25
申请号：US11781054
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：一种执行定时分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的延迟信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

8. 发明申请

US20080052653A1 LITHOGRAPHY AWARE TIMING ANALYSIS 有权
公开(公告)号：US20080052653A1
公开(公告)日：2008-02-28
申请号：US11781054
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：一种执行定时分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的延迟信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

9. 发明授权

US07302661B2 Efficient electromagnetic modeling of irregular metal planes 失效
标题翻译：不规则金属平面的高效电磁建模
公开(公告)号：US07302661B2
公开(公告)日：2007-11-27
申请号：US11152580
申请日：2005-06-14
申请人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与相应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

10. 发明授权

US08572523B2 Lithography aware leakage analysis 有权
标题翻译：光刻感知泄漏分析
公开(公告)号：US08572523B2
公开(公告)日：2013-10-29
申请号：US11781043
申请日：2007-07-20
申请人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
发明人： Emre Tuncer , Hui Zheng , Vivek Raghavan , Anirudh Devgan , Amir Ajami , Alessandra Nardi , Tao Lin , Pramod Thazhathethil , Alfred Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F17/5068 , G06F2217/12
摘要： A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
摘要翻译：执行泄漏分析的方法包括接收指定集成电路的信息。然后确定与集成电路相关联的形状的邻域。基于形状附近生成与集成电路相关联的泄漏信息。可以通过从内部形状确定第一单元的边界的第一组间距来确定形状的邻域。可以从第一单元的边界到第二单元的形状来确定第二组间隔。可以使用第一和第二组间隔来表征光刻工艺。

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