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1. 发明授权

US07827514B2 Efficient electromagnetic modeling of irregular metal planes 有权
标题翻译：不规则金属平面的高效电磁建模
公开(公告)号：US07827514B2
公开(公告)日：2010-11-02
申请号：US11849346
申请日：2007-09-03
申请人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与对应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

2. 发明授权

US07590952B2 Compact chip package macromodels for chip-package simulation 失效
标题翻译：用于芯片封装仿真的紧凑型芯片封装宏模型
公开(公告)号：US07590952B2
公开(公告)日：2009-09-15
申请号：US11563704
申请日：2006-11-28
申请人： Michael W. Beattie , Kevin Beattie, legal representative , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用程序代码以减少芯片封装模型。响应于接收芯片封装模型，测量芯片封装模型的电感和电阻。电感和电阻仅使用芯片封装模型的一组外部节点进行测量。使用芯片封装模型的电感和电阻来创建减少节点电阻器模型和降低节点电感器模型。通过组合减少节点电阻器模型和减少节点电感器模型形成组合的减少节点电阻器 - 电感器芯片封装模型。

3. 发明申请

US20080127010A1 Compact Chip Package Macromodels for Chip-Package Simulation 失效
标题翻译：用于芯片封装模拟的紧凑型芯片封装宏模型
公开(公告)号：US20080127010A1
公开(公告)日：2008-05-29
申请号：US11563704
申请日：2006-11-28
申请人： Michael W. Beattie , Kevin Beattie , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Kevin Beattie , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/40 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
摘要翻译：提供计算机实现的方法，数据处理系统和计算机可用程序代码以减少芯片封装模型。响应于接收芯片封装模型，测量芯片封装模型的电感和电阻。电感和电阻仅使用芯片封装模型的一组外部节点进行测量。使用芯片封装模型的电感和电阻来创建减少节点电阻器模型和降低节点电感器模型。通过组合减少节点电阻器模型和减少节点电感器模型形成组合的减少节点电阻器 - 电感器芯片封装模型。

4. 发明申请

US20080300848A1 EFFICIENT SIMULATION OF DOMINANTLY LINEAR CIRCUITS 审中-公开
标题翻译：高效线性电路的有效仿真
公开(公告)号：US20080300848A1
公开(公告)日：2008-12-04
申请号：US12189813
申请日：2008-08-12
申请人： Michael W. Beattie , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Byron L. Krauter , Hui Zheng
IPC分类号： G06G7/48
CPC分类号： G06F17/5036
摘要： A method of simulating a circuit parameter such as voltage or current for a dominantly linear circuit by constructing a circuit equation matrix whose elements correspond to nodes of the circuit, decoupling linear and nonlinear contributions to the circuit parameter based on a partition of an inverse matrix of the circuit equation matrix, computing linear and nonlinear components using the decoupled contributions, and combining the nonlinear and linear components to yield a state of the circuit parameter for a given time step. The computation of the nonlinear component includes Newton-Raphson iterations to linearize nonlinear devices of the circuit, wherein the Newton-Raphson technique is applied to the right-hand side of the circuit state matrix equation. The computations are iteratively repeated for successive time steps which are advantageously separated by a constant time interval to avoid further recalculation of the state matrix.
摘要翻译：一种通过构造电路方程矩阵来模拟电路参数如电压或电流的方法，该电路方程矩阵的元素对应于电路的节点，基于电路参数的线性和非线性贡献，将基线电路方程矩阵，使用解耦贡献计算线性和非线性分量，以及组合非线性和线性分量以产生给定时间步长的电路参数的状态。非线性分量的计算包括用于线性化电路的非线性器件的Newton-Raphson迭代，其中将Newton-Raphson技术应用于电路状态矩阵方程的右侧。对于连续的时间步长迭代重复计算，这些时间步长有利地以恒定的时间间隔隔开，以避免进一步重新计算状态矩阵。

5. 发明授权

US06820245B2 Methods, systems, and computer program products for modeling inductive effects in a circuit by combining a plurality of localized models 失效
标题翻译：用于通过组合多个局部模型来对电路中的感应效应建模的方法，系统和计算机程序产品
公开(公告)号：US06820245B2
公开(公告)日：2004-11-16
申请号：US10096446
申请日：2002-03-12
申请人： Michael W. Beattie , Lawrence T. Pileggi
发明人： Michael W. Beattie , Lawrence T. Pileggi
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Inductive effects in an integrated circuit device and/or system are modeled by partitioning the integrated circuit device and/or system into multiple windows or portions and determining a first localized inductance matrix for a first portion of the circuit and/or system and a second localized inductance matrix for a second portion of the circuit and/or system. The first and second localized inductance matrices are solved to obtain first and second localized susceptance vectors. The first and second localized susceptance vectors may be combined to form a susceptance matrix, which may be used directly in a susceptance-based simulator, or inverted to obtain a sparser inductance matrix that is representative of the inductive couplings in the entire integrated circuit device and/or system.
摘要翻译：集成电路器件和/或系统中的感应效应通过将集成电路器件和/或系统划分成多个窗口或部分并且确定用于电路和/或系统的第一部分的第一局部电感矩阵和第二局部化用于电路和/或系统的第二部分的电感矩阵。求解第一和第二局部电感矩阵以获得第一和第二局部电纳向量。可以组合第一和第二局部电纳向量以形成电纳矩阵，其可以直接在基于电纳的模拟器中使用或反转，以获得代表整个集成电路装置中的电感耦合的稀疏电感矩阵，以及 /或系统。

6. 发明授权

US07302661B2 Efficient electromagnetic modeling of irregular metal planes 失效
标题翻译：不规则金属平面的高效电磁建模
公开(公告)号：US07302661B2
公开(公告)日：2007-11-27
申请号：US11152580
申请日：2005-06-14
申请人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
发明人： Michael W. Beattie , Anirudh Devgan , Byron L. Krauter , Hui Zheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
摘要翻译：通过将表面划分成不等长且不对齐的矩形的网格，将电路节点位置分配给每个矩形的中心，以及基于中心电路节点位置计算电容和电感参数，来对不规则导电平面中的电磁体进行建模的方法。使用自动递归二分法实现矩形化。电容段被分配给每个电路节点并与相应的矩形重合。感应片段被分配在相邻的矩形对之间，其中感应片段的宽度被定义为相应的一对矩形的公共边界，并且感应片段的长度被定义为两个矩形的电路节点之间的正常距离。电路节点在矩形中心的放置显着减少了节点和节点的数量，并提供了一个更快而又全面的分析框架。

7. 发明授权

US07096174B2 Systems, methods and computer program products for creating hierarchical equivalent circuit models 有权
公开(公告)号：US07096174B2
公开(公告)日：2006-08-22
申请号：US09907334
申请日：2001-07-17
申请人： Michael W. Beattie , Lawrence T. Pileggi
发明人： Michael W. Beattie , Lawrence T. Pileggi
IPC分类号： G06F17/50 , G06G3/10
CPC分类号： G06F17/5036
摘要： Systems, methods and computer program products create an equivalent circuit of electric and/or electronic circuit components, by identifying groups of components and hierarchically modeling aggregate interactions among the groups of components, to create increasingly higher level circuit models, until the equivalent circuit for the components is produced. Hierarchical modeling is provided by defining global components that reflect aggregate parameters of the groups of components and modeling the aggregate interaction among the groups of components as interactions among the global components. Moreover, next higher level global components also are defined that reflect aggregate parameters of at least some of the global components, and the aggregate interaction among the groups of components is modeled as interactions among the next higher level global components. The groups of components may be remote from one another and the hierarchical modeling includes hierarchical modeling of aggregate parasitic couplings among the groups of components.

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