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1. 发明授权

US07837837B2 Magnetic head having high conductivity lead structures seeded by epitaxially matched seed layer and fabrication method therefor 有权
标题翻译：具有通过外延匹配种子层接种的高导电性铅结构的磁头及其制造方法
公开(公告)号：US07837837B2
公开(公告)日：2010-11-23
申请号：US11034351
申请日：2005-01-11
申请人： Michael Andrew Parker , Mustafa Pinarbasi , Robert Otto Schwenker
发明人： Michael Andrew Parker , Mustafa Pinarbasi , Robert Otto Schwenker
IPC分类号： C23C14/16
CPC分类号： B82Y25/00 , G11B5/3133 , G11B5/3163 , G11B5/3903 , G11B5/3967 , H01F10/32 , Y10T29/49025 , Y10T29/49032
摘要： The present invention is directed towards increasing the conductivity of the electrical lead material in the read head portion of a magnetic head, such that thinner electrical leads can be fabricated while the current carrying capacity of the leads is maintained. This increase in electrical lead conductivity is accomplished by fabricating the electrical lead upon an epitaxially matched seed layer, such that the crystalline microstructure of the electrical lead material has fewer grain boundaries, whereby the electrical conductivity of the lead material is increased. In a preferred embodiment, the electrical lead material is comprised of Rh, which has an FCC crystal structure, and the seed layer is comprised of a metal, or metal alloy having a BCC crystal structure with unit cell lattice constant dimensions that satisfy the relationship that abcc is approximately equal to 0.816afcc. In various embodiments, the seed layer is comprised of VMo or VW.
摘要翻译：本发明旨在增加磁头的读头部分中的引线材料的导电性，使得可以在保持导线的载流能力的同时制造更薄的电引线。通过在外延匹配的种子层上制造电引线，使得引线材料的结晶微结构具有更少的晶界，从而提高引线材料的导电性，从而实现电导线导电性的提高。在优选实施例中，电引线材料由具有FCC晶体结构的Rh组成，并且种子层由具有单位晶格恒定尺寸的具有BCC晶体结构的金属或金属合金构成，满足以下关系： abcc大约等于0.816afcc。在各种实施方案中，种子层由VMo或VW组成。

2. 发明授权

US06853519B2 Magnetic head having high conductivity lead structures seeded by epitaxially matched seed layer 失效
标题翻译：具有通过外延匹配种子层接种的高导电性铅结构的磁头
公开(公告)号：US06853519B2
公开(公告)日：2005-02-08
申请号：US10273451
申请日：2002-10-17
申请人： Michael Andrew Parker , Mustafa Pinarbasi , Robert Otto Schwenker
发明人： Michael Andrew Parker , Mustafa Pinarbasi , Robert Otto Schwenker
IPC分类号： G11B5/31 , G11B5/39 , H01F10/32 , G11B5/127
CPC分类号： B82Y25/00 , G11B5/3133 , G11B5/3163 , G11B5/3903 , G11B5/3967 , H01F10/32 , Y10T29/49025 , Y10T29/49032
摘要： The present invention is directed towards increasing the conductivity of the electrical lead material in the read head portion of a magnetic head, such that thinner electrical leads can be fabricated while the current carrying capacity of the leads is maintained. This increase in electrical lead conductivity is accomplished by fabricating the electrical lead upon an epitaxially matched seed layer, such that the crystalline microstructure of the electrical lead material has fewer grain boundaries, whereby the electrical conductivity of the lead material is increased. In a preferred embodiment, the electrical lead material is comprised of Rh, which has an FCC crystal structure, and the seed layer is comprised of a metal, or metal alloy having a BCC crystal structure with unit cell lattice constant dimensions that satisfy the relationship that abcc is approximately equal to 0.816afcc. In various embodiments, the seed layer is comprised of VMo or VW.
摘要翻译：本发明旨在增加磁头的读头部分中的引线材料的导电性，使得可以在保持导线的载流能力的同时制造更薄的电引线。通过在外延匹配的种子层上制造电引线，使得引线材料的结晶微结构具有更少的晶界，从而提高引线材料的导电性，从而实现电导线导电性的提高。在优选实施例中，电引线材料由具有FCC晶体结构的Rh组成，并且种子层由具有单位晶格恒定尺寸的具有BCC晶体结构的金属或金属合金构成，满足以下关系： abcc大约等于0.816afcc。在各种实施方案中，种子层由VMo或VW组成。

3. 发明授权

US06882510B2 Low cost anti-parallel pinned spin valve (SV) and magnetic tunnel junction (MTJ) structures with high thermal stability 有权
标题翻译：具有高热稳定性的低成本反平行钉扎自旋阀（SV）和磁隧道结（MTJ）结构
公开(公告)号：US06882510B2
公开(公告)日：2005-04-19
申请号：US10254345
申请日：2002-09-24
申请人： Michael Andrew Parker , Robert Otto Schwenker
发明人： Michael Andrew Parker , Robert Otto Schwenker
IPC分类号： G01R33/09 , G11B5/00 , G11B5/31 , G11B5/39 , H01F10/32
CPC分类号： B82Y25/00 , B82Y10/00 , G01R33/093 , G01R33/098 , G11B5/313 , G11B5/3903 , G11B5/3909 , G11B2005/0008 , G11B2005/3996 , H01F10/3254 , H01F10/3272
摘要： The invention is a laminated antiferromagnetically coupled (AFC) structure for use in a spin valve (SV) sensor or magnetic tunnel junction (MTJ) device, having two ferromagnetic films coupled together with an improved AFC film. Particularly the AFC film comprises an alloy material selected from the group consisting of Ru100-xmx, Os100-ymy, Ir100-ymy, Rh100-y,my, Re100-zmz, and M100-xmx, where M is an alloy of two or more materials selected from the group consisting of Ru, Os, Ir, Rh, and Re, and where m is a material selected from the group consisting of W, Ta, Mo, Nb and alloys of two or more materials selected from W, Ta, Mo, and Nb, and where x is between approximately 5 and 95 at. %, y is between approximately 10 and 90 at. %, and z is between approximately 25 and 75 at. %. The sensors may be used in magnetic heads of hard disk drives.
摘要翻译：本发明是一种用于自旋阀（SV）传感器或磁性隧道结（MTJ）装置）的层叠反铁磁耦合（AFC）结构，其具有与改进的AFC膜耦合在一起的两个铁磁膜。特别地，AFC膜包括选自以下的合金材料：Ru 100-x M x x，O a 100-y m， y 100，y 100 y y，y 100 y y，m y y，Re 其中M是两个或两个或更多个的合金，其中M是两个或更多个的合金，更多选自Ru，Os，Ir，Rh和Re的材料，其中m是选自W，Ta，Mo，Nb的材料，以及选自W，Ta的两种或更多种材料的合金，Mo和Nb，并且其中x在约5和95at之间。％，y在约10和90之间。％，z在约25和75之间。％传感器可用于硬盘驱动器的磁头。

4. 发明授权

US06519118B2 Read head with read track width defining layer that planarizes the write gap layer of a write head 失效
公开(公告)号：US06519118B2
公开(公告)日：2003-02-11
申请号：US10094913
申请日：2002-03-11
申请人： Henry C. Chang , Cherngye Hwang , Robert Otto Schwenker
发明人： Henry C. Chang , Cherngye Hwang , Robert Otto Schwenker
IPC分类号： G11B5127
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/012 , G11B5/3116 , G11B5/3163 , G11B5/3903 , G11B5/3932 , G11B5/3967 , G11B2005/3996 , Y10T29/49025 , Y10T29/49032 , Y10T29/49041 , Y10T29/49044 , Y10T29/4905 , Y10T29/49052
摘要： A read track width defining layer is employed for defining first and second side edges of a read sensor. The read track width defining layer preferably remains in the head to planarize the read head at first and second hard bias and lead layers so as to overcome a problem of write gap curvature in an accompanying write head. The read track width defining layer is defined by a subtractive process about a bilayer photoresist layer. The subtractive process is selective to the read track width defining layer over a read sensor material layer therebelow. Ion milling is then employed for defining first and second side edges of a read sensor layer employing the read track width defining layer as a mask. First and second hard bias and lead layers are then deposited which make contiguous junctions with the first and second side edges of each of the read sensor and read track width defining layers. The photoresist is then removed and the remainder of the read head is completed.

5. 发明授权

US4076558A Method of high current ion implantation and charge reduction by simultaneous kerf implant 失效
标题翻译：高电流离子注入和同步切口植入电荷还原的方法
公开(公告)号：US4076558A
公开(公告)日：1978-02-28
申请号：US763789
申请日：1977-01-31
申请人： Hans Stephen Rupprecht , Robert Otto Schwenker
发明人： Hans Stephen Rupprecht , Robert Otto Schwenker
IPC分类号： H01L29/73 , G01Q70/00 , H01L21/265 , H01L21/3115 , H01L21/331 , H01L21/78 , H01L21/425 , H01L21/461
CPC分类号： H01L21/265 , H01L21/31155 , H01L21/78
摘要： A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.
摘要翻译：提供了一种离子注入方法，其特别适用于利用具有至少0.5ma电流的离子束的具有高电流离子注入装置的集成电路的制造。该方法避免了半导体晶圆表面上过多的电荷积累，这可能破坏表面电绝缘，从而使集成电路无效。该方法包括在晶片上形成电绝缘材料层，多个开口穿过各种芯片区域中的绝缘层，以暴露待离子注入导电性确定杂质的半导体晶片表面，此外，在晶片芯片之间的切口区域上形成穿过绝缘层的开口，以露出与切屑开口相邻的晶片切口。在晶片切口中暴露的总面积必须大于在所述芯片晶片开口中露出的总面积。然后，具有足够能量以在所述芯片区域和切口开口中暴露的晶片中注入离子的离子束被引导到晶片。切口开口的存在避免了电荷积聚的问题。然后，通过常规切割去除切口区域，以将晶片分离成多个芯片。

6. 发明授权

US06434814B1 Method of manufacturing a magnetic head including a read head with read track width defining layer that planarizes the write gap layer of a write head 失效
标题翻译：一种制造磁头的方法，该磁头包括具有读磁道宽度限定层的读头，平面化写头的写间隙层
公开(公告)号：US06434814B1
公开(公告)日：2002-08-20
申请号：US09212724
申请日：1998-12-16
申请人： Henry C. Chang , Cherngye Hwang , Robert Otto Schwenker
发明人： Henry C. Chang , Cherngye Hwang , Robert Otto Schwenker
IPC分类号： G11B5127
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/012 , G11B5/3116 , G11B5/3163 , G11B5/3903 , G11B5/3932 , G11B5/3967 , G11B2005/3996 , Y10T29/49025 , Y10T29/49032 , Y10T29/49041 , Y10T29/49044 , Y10T29/4905 , Y10T29/49052
摘要： A method of making a magnetic head that has a read head with a track width includes the steps of depositing a read track width defining material layer on a read sensor material layer; forming a bi-layer photoresist mask on the read track width defining material layer that masks a read track width defining layer portion of the read track width defining material layer; removing by reactive ion etching (RIE) a portion of the read track width defining material layer not masked by the photoresist mask to form the read track width defining layer portion with exposed first and second side edges that are spaced apart a distance equal to the track width; removing by ion milling a first portion of the read sensor material layer not masked by the read track width defining layer portion to form a second portion of the read sensor material layer with exposed first and second side edges that have a width equal to the track width; depositing hard bias and lead material layers on the photoresist mask in contact with the first and second side edges of each of the second portion of the read sensor material layer and the read track width defining layer portion; and removing the photoresist mask, thereby lifting off a portion of the hard bias and lead material layers leaving first and second hard bias and lead layers connected to the first and second side edges of each of the second portion of the read sensor material layer and the read track width defining layer portion.
摘要翻译：制造具有带磁道宽度的读头的磁头的方法包括以下步骤：在读取的传感器材料层上沉积限定材料层的读取磁道宽度; 在所述读取磁道宽度限定材料层上形成双层光致抗蚀剂掩模，其掩蔽所述读取磁道宽度限定材料层的读取磁道宽度限定层部分; 通过反应离子蚀刻（RIE）去除未被光致抗蚀剂掩模掩蔽的读磁道宽度限定材料层的一部分，以形成具有暴露的第一和第二侧边缘，该第一和第二侧边缘间隔开等于轨道的距离宽度; 通过离子研磨读取的传感器材料层的第一部分而不被读取磁道宽度限定层部分掩蔽，以形成具有等于轨道宽度的宽度的暴露的第一和第二侧边缘的读取传感器材料层的第二部分 ; 在所述光致抗蚀剂掩模上沉积与所述读取传感器材料层的第二部分和所述读取磁道宽度限定层部分中的每一个的第一和第二侧边缘接触的硬偏压和引线材料层; 并且去除光致抗蚀剂掩模，从而剥离硬偏压和引线材料层的一部分，留下第一和第二硬偏压和引线层，其连接到读取传感器材料层的第二部分的第一和第二侧边缘，并且读取磁道宽度定义层部分。

7. 发明授权

US4118250A Process for producing integrated circuit devices by ion implantation 失效
标题翻译：通过离子注入制造集成电路器件的工艺
公开(公告)号：US4118250A
公开(公告)日：1978-10-03
申请号：US865805
申请日：1977-12-30
申请人： Cheng Tzong Horng , Alwin Earl Michel , Hans Stephan Rupprecht , Robert Otto Schwenker
发明人： Cheng Tzong Horng , Alwin Earl Michel , Hans Stephan Rupprecht , Robert Otto Schwenker
IPC分类号： H01L29/73 , H01L21/033 , H01L21/265 , H01L21/331 , H01L21/76 , H01L21/223
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/26513 , H01L21/2652
摘要： In this process of producing a bipolar transistor, all the regions of the device except the emitter region are formed by ion implantation through an inorganic dielectric layer of uniform thickness. Subsequently, all the contact openings to the emitter, base and collector are formed and the emitter is implanted through the emitter contact opening. This unique combination of process steps permits the use of a surface insulating dielectric layer of uniform thickness, wherein all capacitances are uniform and controllable while still permitting direct implantation of the emitter, which, because of its shallow depth is difficult to implant through an oxide.
摘要翻译：在制造双极型晶体管的过程中，除了发射极区域之外的器件的所有区域通过通过均匀厚度的无机介电层的离子注入而形成。随后，形成到发射极，基极和集电极的所有接触开口，并通过发射极接触开口注入发射极。这种独特的工艺步骤的组合允许使用均匀厚度的表面绝缘电介质层，其中所有电容均匀和可控，同时仍然允许发射器的直接注入，由于其浅的深度难以通过氧化物注入。

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