会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Method of high current ion implantation and charge reduction by
simultaneous kerf implant
    • 高电流离子注入和同步切口植入电荷还原的方法
    • US4076558A
    • 1978-02-28
    • US763789
    • 1977-01-31
    • Hans Stephen RupprechtRobert Otto Schwenker
    • Hans Stephen RupprechtRobert Otto Schwenker
    • H01L29/73G01Q70/00H01L21/265H01L21/3115H01L21/331H01L21/78H01L21/425H01L21/461
    • H01L21/265H01L21/31155H01L21/78
    • A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical insulation, thereby rendering the integrated circuit ineffective. The method involves forming in a layer of electrically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impurities, and in addition, forming openings through the insulative layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the exposed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.
    • 提供了一种离子注入方法,其特别适用于利用具有至少0.5ma电流的离子束的具有高电流离子注入装置的集成电路的制造。 该方法避免了半导体晶圆表面上过多的电荷积累,这可能破坏表面电绝缘,从而使集成电路无效。 该方法包括在晶片上形成电绝缘材料层,多个开口穿过各种芯片区域中的绝缘层,以暴露待离子注入导电性确定杂质的半导体晶片表面,此外, 在晶片芯片之间的切口区域上形成穿过绝缘层的开口,以露出与切屑开口相邻的晶片切口。 在晶片切口中暴露的总面积必须大于在所述芯片晶片开口中露出的总面积。 然后,具有足够能量以在所述芯片区域和切口开口中暴露的晶片中注入离子的离子束被引导到晶片。 切口开口的存在避免了电荷积聚的问题。 然后,通过常规切割去除切口区域,以将晶片分离成多个芯片。
    • 6. 发明授权
    • Method of manufacturing a magnetic head including a read head with read track width defining layer that planarizes the write gap layer of a write head
    • 一种制造磁头的方法,该磁头包括具有读磁道宽度限定层的读头,平面化写头的写间隙层
    • US06434814B1
    • 2002-08-20
    • US09212724
    • 1998-12-16
    • Henry C. ChangCherngye HwangRobert Otto Schwenker
    • Henry C. ChangCherngye HwangRobert Otto Schwenker
    • G11B5127
    • B82Y25/00B82Y10/00G11B5/012G11B5/3116G11B5/3163G11B5/3903G11B5/3932G11B5/3967G11B2005/3996Y10T29/49025Y10T29/49032Y10T29/49041Y10T29/49044Y10T29/4905Y10T29/49052
    • A method of making a magnetic head that has a read head with a track width includes the steps of depositing a read track width defining material layer on a read sensor material layer; forming a bi-layer photoresist mask on the read track width defining material layer that masks a read track width defining layer portion of the read track width defining material layer; removing by reactive ion etching (RIE) a portion of the read track width defining material layer not masked by the photoresist mask to form the read track width defining layer portion with exposed first and second side edges that are spaced apart a distance equal to the track width; removing by ion milling a first portion of the read sensor material layer not masked by the read track width defining layer portion to form a second portion of the read sensor material layer with exposed first and second side edges that have a width equal to the track width; depositing hard bias and lead material layers on the photoresist mask in contact with the first and second side edges of each of the second portion of the read sensor material layer and the read track width defining layer portion; and removing the photoresist mask, thereby lifting off a portion of the hard bias and lead material layers leaving first and second hard bias and lead layers connected to the first and second side edges of each of the second portion of the read sensor material layer and the read track width defining layer portion.
    • 制造具有带磁道宽度的读头的磁头的方法包括以下步骤:在读取的传感器材料层上沉积限定材料层的读取磁道宽度; 在所述读取磁道宽度限定材料层上形成双层光致抗蚀剂掩模,其掩蔽所述读取磁道宽度限定材料层的读取磁道宽度限定层部分; 通过反应离子蚀刻(RIE)去除未被光致抗蚀剂掩模掩蔽的读磁道宽度限定材料层的一部分,以形成具有暴露的第一和第二侧边缘,该第一和第二侧边缘间隔开等于轨道的距离 宽度; 通过离子研磨读取的传感器材料层的第一部分而不被读取磁道宽度限定层部分掩蔽,以形成具有等于轨道宽度的宽度的暴露的第一和第二侧边缘的读取传感器材料层的第二部分 ; 在所述光致抗蚀剂掩模上沉积与所述读取传感器材料层的第二部分和所述读取磁道宽度限定层部分中的每一个的第一和第二侧边缘接触的硬偏压和引线材料层; 并且去除光致抗蚀剂掩模,从而剥离硬偏压和引线材料层的一部分,留下第一和第二硬偏压和引线层,其连接到读取传感器材料层的第二部分的第一和第二侧边缘,并且 读取磁道宽度定义层部分。