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1. 发明授权

US5708391A High frequency differential filter with CMOS control 失效
标题翻译：具有CMOS控制的高频差分滤波器
公开(公告)号：US5708391A
公开(公告)日：1998-01-13
申请号：US643140
申请日：1996-05-02
申请人： Michael Altmann , Bernard Guay
发明人： Michael Altmann , Bernard Guay
IPC分类号： H03H11/12 , H03F3/45 , H03F3/191
CPC分类号： H03H11/1291 , H03H11/1213 , H03F2203/45504 , H03F2203/7203
摘要： A programmable high frequency active filter comprises a plurality of basic building blocks connected in parallel. A basic building block includes a transistor pair connected in a differential amplifier configuration, an impedance connected between the emitters of the transistors and a switching block for applying the necessary bias current to the transistors. The transfer function of the filter is programmed with a digital word, the length of which determines the number of basic building blocks included in the configuration. In this way, the equivalent high frequency impedance of the filter is controlled by selecting the configuration and the value of the impedance of each building block.
摘要翻译：可编程高频有源滤波器包括并联连接的多个基本构建块。基本构建块包括连接在差分放大器配置中的晶体管对，连接在晶体管的发射极之间的阻抗和用于将必要的偏置电流施加到晶体管的开关块。滤波器的传递函数用数字字编程，数字字的长度决定了配置中包含的基本构件的数量。以这种方式，通过选择每个结构单元的阻抗的配置和值来控制滤波器的等效高频阻抗。

2. 发明授权

US5420529A Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals 失效
标题翻译：电流转向开关和混合BiCMOS多路复用器，具有CMOS换向信号和CML / ECL数据信号
公开(公告)号：US5420529A
公开(公告)日：1995-05-30
申请号：US246207
申请日：1994-05-19
申请人： Bernard Guay , Michael Altmann
发明人： Bernard Guay , Michael Altmann
IPC分类号： H03K17/62 , H03K17/693 , H03K19/094
CPC分类号： H03K17/6292 , H03K17/693
摘要： A current steering switch circuit responsive to a CMOS signal. In an specific embodiment the switch is incorporated in a hybrid BiCMOS multiplexer circuit using combined CMOS and CML/ECL signal types. The high speed CML/ECL logic signals are multiplexed under the control of a lower speed CMOS signal. A particular aspect of the circuit is that a CMOS to CML/ECL converter is not used. Additionally, a differential, logic commutation signal is not required.
摘要翻译：响应于CMOS信号的电流转向开关电路。在具体实施例中，使用组合的CMOS和CML / ECL信号类型将开关并入混合BiCMOS多路复用器电路。高速CML / ECL逻辑信号在低速CMOS信号的控制下被复用。电路的一个特定方面是不使用CMOS到CML / ECL转换器。此外，不需要差分逻辑换向信号。

3. 发明授权

US5945860A CLM/ECL clock phase shifter with CMOS digital control 失效
标题翻译：具有CMOS数字控制的CLM / ECL时钟移相器
公开(公告)号：US5945860A
公开(公告)日：1999-08-31
申请号：US583169
申请日：1996-01-04
申请人： Bernard Guay , Michael Altmann
发明人： Bernard Guay , Michael Altmann
IPC分类号： H03C1/54 , H03K5/151 , H03K5/13 , H03K3/00
CPC分类号： H03C1/542 , H03K5/151
摘要： A CML/ECL clock phase shifter device provides a 360.degree. phase control range and, upon being provided with two CML clock signals related by a known phase difference, the device produces any desired phase in response to a control signal. The device uses a CMOS current switch which generates current signals having the amplitude adjustable with the control signal, which is a digital word. Differential pairs provide amplitude modulated current signals for the input clock and the variant of the input clock. Two MOS transmission networks selectively invert each amplitude modulated signal and sum the signals from each side on a load network. The phase control resolution is optimal over four quadrants for quadrature input clock signals.
摘要翻译： CML / ECL时钟移相器装置提供360°相位控制范围，并且在被提供有与已知相位差相关的两个CML时钟信号时，该装置响应于控制信号产生任何期望的相位。该器件使用CMOS电流开关，其产生具有作为数字字的控制信号可调幅度的电流信号。差分对为输入时钟和输入时钟的变体提供幅度调制电流信号。两个MOS传输网络选择性地反转每个幅度调制信号，并且在负载网络上对来自每一侧的信号求和。正交输入时钟信号的四个象限的相位控制分辨率是最佳的。

4. 发明授权

US5825825A Method of processing multi-level signals for simple clock recovery 失效
标题翻译：处理多电平信号的简单时钟恢复方法
公开(公告)号：US5825825A
公开(公告)日：1998-10-20
申请号：US715218
申请日：1996-09-17
申请人： Michael Altmann , Bernard Guay
发明人： Michael Altmann , Bernard Guay
IPC分类号： H03K5/1532 , H04L7/033 , H04L25/49
CPC分类号： H03K5/1532 , H04L7/007 , H04L7/0331
摘要： A method and a circuit for simple clock recovery from multi-level at high transmission rates. The circuit is compatible with standard PLL-type clock recovery techniques for NRZ and generalized two-level signalling. The timing information is extracted from a single threshold crossing, irrespective of the number of levels (M) of the signal. This was verified to provide sufficient spectral information for the proper operation of a clock recovery PLL. The threshold may be programmed for various line codes.
摘要翻译：一种用于以高传输速率从多级简单时钟恢复的方法和电路。该电路与NRZ的标准PLL类型时钟恢复技术和广义的两级信号兼容。不考虑信号的电平（M）的数量，从单个阈值交叉提取定时信息。这被验证为提供足够的频谱信息用于时钟恢复PLL的正确操作。阈值可以针对各种线路代码进行编程。

5. 发明授权

US07885368B2 Analog phase controller 有权
标题翻译：模拟相位控制器
公开(公告)号：US07885368B2
公开(公告)日：2011-02-08
申请号：US11479411
申请日：2006-06-30
申请人： Michael Altmann
发明人： Michael Altmann
IPC分类号： H03D3/24
CPC分类号： H03L7/089 , H03L7/0812 , H03L7/093
摘要： Disclosed are embodiments of a phase control circuit with an analog phase controller that is able to effectively generate control signals for all four quadrants of phase control operation.
摘要翻译：公开了具有模拟相位控制器的相位控制电路的实施例，其能够有效地产生用于所有四个相位控制运算的象限的控制信号。

6. 发明申请

US20070236258A1 Current-balanced logic circuit 有权
标题翻译：电流平衡逻辑电路
公开(公告)号：US20070236258A1
公开(公告)日：2007-10-11
申请号：US11390180
申请日：2006-03-28
申请人： Kursad Kiziloglu , Michael Altmann
发明人： Kursad Kiziloglu , Michael Altmann
IPC分类号： H03F3/45
CPC分类号： G11C7/1078 , G11C7/062 , G11C7/08 , G11C7/1096
摘要： In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.
摘要翻译：根据一些实施例，电流平衡逻辑电路包括第一读出放大器，第二读出放大器和向第一和第二读出放大器提供偏置电流的电流源晶体管。第一和第二读出放大器由第一和第二差分时钟信号交替地激活，并且当被激活时将在差分输入线上接收的数据转换成逻辑值以存储在相应的存储电路中。存储电路可以是触发器，锁存器，保持器电路或用于存储数据的其他电路。

7. 发明申请

US20080002800A1 Analog phase controller 有权
标题翻译：模拟相位控制器
公开(公告)号：US20080002800A1
公开(公告)日：2008-01-03
申请号：US11479411
申请日：2006-06-30
申请人： Michael Altmann
发明人： Michael Altmann
IPC分类号： H03D3/24
CPC分类号： H03L7/089 , H03L7/0812 , H03L7/093
摘要： Disclosed are embodiments of a phase control circuit with an analog phase controller that is able to effectively generate control signals for all four quadrants of phase control operation.
摘要翻译：公开了具有模拟相位控制器的相位控制电路的实施例，其能够有效地产生用于所有四个相位控制操作象限的控制信号。

8. 发明申请

US20100198609A1 SYSTEMS, METHODS AND APPARATUSES FOR PREDICTING CAPACITY OF RESOURCES IN AN INSTITUTION 有权
标题翻译：用于预测机构资源能力的系统，方法和装置
公开(公告)号：US20100198609A1
公开(公告)日：2010-08-05
申请号：US12363954
申请日：2009-02-02
申请人： Andrew Mellin , Keith Willard , Catherine Whelchel , Mike Myers , Kristin Oswald , Michael Altmann
发明人： Andrew Mellin , Keith Willard , Catherine Whelchel , Mike Myers , Kristin Oswald , Michael Altmann
IPC分类号： G06Q50/00
CPC分类号： G06Q50/22 , G06F19/00 , G06Q10/00 , G06Q10/06 , G06Q10/0637 , G06Q10/0639 , G16H40/20
摘要： A method, apparatus, system and computer program product are provided for determining one or more current or future conditions regarding capacity and allocation of resources in an institution. The apparatus enables personnel to utilize predictive tools to identify in real-time or in the near future areas of capacity constraints within the institution. The apparatus includes a processor configured to analyze data which includes information associated with the institution. A portion of the data is generated in real-time during an actual time in which events occur. The processor is capable of using at least a portion of the data to identify current conditions or generate one or more predictions regarding conditions to occur in the future that are associated with resources and capacity of the institution. Also, the processor is capable of analyzing results of the predictions and allocating resources of the institution on the basis of the predicted results.
摘要翻译：提供了一种方法，装置，系统和计算机程序产品，用于确定关于机构中的资源的容量和分配的一个或多个当前或将来的条件。该装置使得人员能够利用预测工具来实时地或在不久的将来在该机构内的容量限制区域中识别。该装置包括处理器，其被配置为分析包括与机构相关联的信息的数据。数据的一部分在实际发生事件的时间内实时生成。处理器能够使用至少一部分数据来识别当前条件，或者产生关于将来发生的与机构的资源和能力相关的条件的一个或多个预测。此外，处理器能够根据预测结果分析预测结果并分配机构的资源。

9. 发明授权

US07498889B2 Analog phase controller 有权
标题翻译：模拟相位控制器
公开(公告)号：US07498889B2
公开(公告)日：2009-03-03
申请号：US11499028
申请日：2006-08-03
申请人： Michael Altmann
发明人： Michael Altmann
IPC分类号： H03L7/08
CPC分类号： H03L7/093 , H03L7/0812 , H03L7/0893
摘要： Disclosed are embodiments of a phase control circuit with an analog phase controller having first and second order integration. In some embodiments, the analog control circuit generates first and second control signals and controls the first control signal based on the sign of the second control signal and controls the second control signal based on the sign of the first control signal.
摘要翻译：公开了具有具有一阶和二阶积分的模拟相位控制器的相位控制电路的实施例。在一些实施例中，模拟控制电路产生第一和第二控制信号，并且基于第二控制信号的符号来控制第一控制信号，并且基于第一控制信号的符号来控制第二控制信号。

10. 发明授权

US5219989A Bifunctional protein for the isolation of capped mRNA 失效
标题翻译：双功能蛋白用于分离上限mRNA
公开(公告)号：US5219989A
公开(公告)日：1993-06-15
申请号：US840565
申请日：1992-02-24
申请人： Nahum Sonenberg , Isaac Edery , Michael Altmann
发明人： Nahum Sonenberg , Isaac Edery , Michael Altmann
IPC分类号： C07K14/31 , C07K14/395 , C12N15/10
CPC分类号： C12N15/1096 , C07K14/31 , C07K14/395 , C07K2319/705
摘要： A protein comprising at least a first functional site having the ability to bind the cap structure of mRNA and a second functional site having the ability to bind a solid support matrix in such a manner as to allow the first functional site to be immobilized and still remain functionally accessible to interact with the cap structure of mRNA. Also within the scope of the present invention is a method for generating a cDNA library mostly containing full-length cDNAs. The method comprises the incubation of a mixture comprising mRNA:cDNA hybrids with 1) a single strand RNA specific nuclease and 2) the above-mentioned protein. The resulting mixture is then passed through a column comprising a support matrix having the ability to bind the second functional site of the above-mentioned protein in order to selectively bind complete mRNA:cDNA hybrids. The mRNA:cDNA hybrids are then competitively eluted with a cap analog and full-length cDNA strands are separated and recovered. The present invention also includes a method for purifying capped mRNA using the above-mentioned protein. The process comprises the incubation of a mixture containing mRNA with the above-mentioned protein, passing the resulting mixture through a column comprising the support matrix having the ability to bind to the second functional site of the above-mentioned protein in order to selectively bind capped mRNAs, and competitively eluting the capped mRNAs with a cap analog.
摘要翻译：包含至少具有结合mRNA的帽结构的能力的第一功能部位的蛋白质和具有结合固体支持体基质的能力的第二功能部位，以允许第一功能部位被固定并仍然保持功能上可与mRNA的帽结构相互作用。也在本发明范围内的是产生大部分含有全长cDNA的cDNA文库的方法。该方法包括将包含mRNA：cDNA杂交体的混合物与1）单链RNA特异性核酸酶和2）上述蛋白质的孵育。然后将所得混合物通过包含具有结合上述蛋白质的第二功能位点的能力的载体基质的柱，以便选择性地结合完整的mRNA：cDNA杂交体。然后用盖类似物竞争性地洗脱mRNA：cDNA杂交体，并分离并回收全长cDNA链。本发明还包括使用上述蛋白质纯化封闭mRNA的方法。该方法包括将含有mRNA的混合物与上述蛋白质孵育，使所得混合物通过包含能够结合上述蛋白质的第二功能位点的载体基质的柱，以选择性地结合封端 mRNA，并用帽类似物竞争性洗脱加盖的mRNA。

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