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1. 发明申请

US20120245724A1 PASSIVE RESONATOR, A SYSTEM INCORPORATING THE PASSIVE RESONATOR FOR REAL-TIME INTRA-PROCESS MONITORING AND CONTROL AND AN ASSOCIATED METHOD 失效
标题翻译：被动谐振器，用于实时监控和控制的被动共振器的系统和相关方法
公开(公告)号：US20120245724A1
公开(公告)日：2012-09-27
申请号：US13052346
申请日：2011-03-21
申请人： Mete Erturk , Ezra D.B. Hall , Kirk D. Peterson
发明人： Mete Erturk , Ezra D.B. Hall , Kirk D. Peterson
IPC分类号： H01L29/66 , G06F19/00
CPC分类号： H01L22/14 , H01L22/26 , H01L23/5227 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).
摘要翻译：公开了由半导体层的三个部分（即第一，第二和第三部分）构成的谐振器。第二部分具有邻接第一部分的端部，围绕第一部分卷绕的中间部分（即电感器部分），以及抵靠第三部分的另一端部。与第二部分相比，第一和第三部分显示比晶片衬底更高的电容。还公开了并入这些谐振器中的一个或多个的过程控制系统和方法。具体地，在处理工具的处理期间，无线询问单元响应于所施加的刺激来检测谐振器的频率响应。测量检测到的频率响应并将其用作对处理工具上的输入设置进行实时调整的基础（例如，作为对退火室的温度设置进行实时调整的基础）。

2. 发明授权

US08700199B2 Passive resonator, a system incorporating the passive resonator for real-time intra-process monitoring and control and an associated method 失效
标题翻译：无源谐振器，一种结合无源谐振器的实时内部监控和控制系统及相关方法
公开(公告)号：US08700199B2
公开(公告)日：2014-04-15
申请号：US13052346
申请日：2011-03-21
申请人： Mete Erturk , Ezra D. B. Hall , Kirk D. Peterson
发明人： Mete Erturk , Ezra D. B. Hall , Kirk D. Peterson
IPC分类号： G06F19/00
CPC分类号： H01L22/14 , H01L22/26 , H01L23/5227 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).
摘要翻译：公开了由半导体层的三个部分（即第一，第二和第三部分）构成的谐振器。第二部分具有邻接第一部分的端部，围绕第一部分卷绕的中间部分（即电感器部分），以及抵靠第三部分的另一端部。与第二部分相比，第一和第三部分显示比晶片衬底更高的电容。还公开了并入这些谐振器中的一个或多个的过程控制系统和方法。具体地，在处理工具的处理期间，无线询问单元响应于所施加的刺激来检测谐振器的频率响应。检测到的频率响应被测量并用作对处理工具上的输入设置进行实时调整的基础（例如，作为对退火室的温度设置进行实时调整的基础）。

3. 发明申请

US20130249052A1 CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE 有权
标题翻译：在基础上创建深度倾斜
公开(公告)号：US20130249052A1
公开(公告)日：2013-09-26
申请号：US13428004
申请日：2012-03-23
申请人： Jennifer E. Appleyard , John E. Barth, JR. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
发明人： Jennifer E. Appleyard , John E. Barth, JR. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L21/76898 , H01L27/0805 , H01L28/91 , H01L29/945
摘要： A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
摘要翻译：公开了半导体结构及其制造方法。在一个实施例中，该结构包括在衬底中具有掩埋板或板的第一衬底。每个掩埋板包括至少一个掩埋板触点和围绕至少一个掩埋板触点设置的多个深沟槽电容器。第一氧化物层设置在第一衬底上。可以访问第一衬底中的深沟槽电容器和掩埋板触点，以用于各种存储器和去耦应用。

4. 发明申请

US20130200910A1 3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS 有权
标题翻译：采用微机电开关的三维集成电路测试
公开(公告)号：US20130200910A1
公开(公告)日：2013-08-08
申请号：US13364345
申请日：2012-02-02
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G01R1/067 , H01L21/768
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译：一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

5. 发明授权

US08470713B2 Nitride etch for improved spacer uniformity 失效
标题翻译：氮化物蚀刻用于改善间隔物均匀性
公开(公告)号：US08470713B2
公开(公告)日：2013-06-25
申请号：US12966432
申请日：2010-12-13
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/76237 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L29/78
摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
摘要翻译：一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

6. 发明申请

US20120066657A1 METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE 有权
标题翻译：基于可制造性，测试覆盖和可选择的诊断覆盖的组合设计集成电路的方法
公开(公告)号：US20120066657A1
公开(公告)日：2012-03-15
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

7. 发明授权

US08120141B2 Method and structure to prevent circuit network charging during fabrication of integrated circuits 失效
标题翻译：在集成电路制造过程中防止电路网络充电的方法和结构
公开(公告)号：US08120141B2
公开(公告)日：2012-02-21
申请号：US11687711
申请日：2007-03-19
申请人： Jeffrey P. Gambino , Kirk D. Peterson
发明人： Jeffrey P. Gambino , Kirk D. Peterson
IPC分类号： H01L21/00 , H01L21/82
CPC分类号： H01L27/1203 , H01L23/5256 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.
摘要翻译：集成电路及其制造方法。该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络，更多数据网络及其组合。

8. 发明申请

US20110208482A1 Variable Focus Point Lens 有权
标题翻译：可变焦点镜头
公开(公告)号：US20110208482A1
公开(公告)日：2011-08-25
申请号：US12708561
申请日：2010-02-19
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G06F17/50 , G02B3/12
CPC分类号： G02B3/14
摘要： A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.
摘要翻译：可变焦点透镜包括透明容器，透明容器包括透明的外壳，该透明外壳包含将透明容器的内部容积分隔成上部容器部分和下部容器部分的透明柔性膜。上罐部分和下罐部分含有不同折射率的液体。透明柔性膜被静电移位以改变光路中的第一罐部分和第二罐部分的厚度，从而轴向和/或横向地移动透镜的焦点。膜的静电位移可以通过膜中的固定电荷和透明外壳上的封闭侧导电结构阵列，或透明膜上的膜侧导电结构阵列和外壳侧阵列导电结构。

9. 发明授权

US07948535B2 High dynamic range imaging cell with electronic shutter extensions 有权
标题翻译：具有电子快门延伸功能的高动态范围成像单元
公开(公告)号：US07948535B2
公开(公告)日：2011-05-24
申请号：US11948463
申请日：2007-11-30
申请人： John J. Ellis-Monaghan , Alain Loiseau , Kirk D. Peterson
发明人： John J. Ellis-Monaghan , Alain Loiseau , Kirk D. Peterson
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/37452 , H04N5/35527 , H04N5/3559
摘要： A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation.
摘要翻译：提供了改进的动态范围的像素传感器单元和包括体现在机器可读介质中的像素传感器单元的设计结构。像素单元包括将电容器器件耦合到像素单元的光敏区域（例如，光电二极管）的耦合晶体管，光电二极管耦合到传输栅极和耦合晶体管的一个端子。在操作中，当光电二极管上的电压向下拉到衬底电位时，附加电容耦合到像素单元光电二极管。因此，当电池接近其充电容量时，所添加的电容仅连接到成像器单元。否则，电池具有低电容和低泄漏。在另外的实施例中，电容器的端子耦合到“脉冲”电源电压信号，其在像素传感器单元的读出操作期间使存储的电荷从电容器到光敏区域基本上完全耗尽。在各种实施例中，增加的电容和光电二极管的位置可以相对于耦合晶体管互换。此外，像素传感器单元的附加电容允许全局快门操作。

10. 发明申请

US20110098838A1 SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS 有权
标题翻译：用于校正集成电路芯片的系统参数变化的系统和方法，以最小化电路有限的损失
公开(公告)号：US20110098838A1
公开(公告)日：2011-04-28
申请号：US12603679
申请日：2009-10-22
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.
摘要翻译：公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。存储处理信息和芯片的映射。处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。地图可以指示设备参数中的区域变化（例如，阈值电压）。基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。

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