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1. 发明申请

US20120066657A1 METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE 有权
标题翻译：基于可制造性，测试覆盖和可选择的诊断覆盖的组合设计集成电路的方法
公开(公告)号：US20120066657A1
公开(公告)日：2012-03-15
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

2. 发明申请

US20110199114A1 BIT FAILURE SIGNATURE IDENTIFICATION 有权
标题翻译：位错误标识识别
公开(公告)号：US20110199114A1
公开(公告)日：2011-08-18
申请号：US12706228
申请日：2010-02-16
申请人： Thomas D. Furland , Robert J. Milne , Leah M.P. Pastel , Kevin W. Stanley , Robert C. Virun
发明人： Thomas D. Furland , Robert J. Milne , Leah M.P. Pastel , Kevin W. Stanley , Robert C. Virun
IPC分类号： G01R31/26
CPC分类号： G01R31/31703 , G01R31/31935
摘要： A method, system, and program product for identifying at least one bit failure among a plurality of semiconductor chips are provided. A first aspect of the invention provides a method of identifying at least one bit failure signature among a plurality of semiconductor chips, the method comprising: counting failures of each failing bit among the plurality of semiconductor chips; determining a most commonly failing bit (MCFB) among the failing bits; establishing a bit failure signature including the MCFB; counting failures of each failing bit on semiconductor chips on which the MCFB fails; determining a next most commonly failing bit (NMCFB) among the failing bits on semiconductor chips on which the MCFB fails; determining whether the NMCFB tends to fail when the MCFB fails; and in response to a determination that the NMCFB tends to fail when the MCFB fails, adding the NMCFB to the bit failure signature.
摘要翻译：提供了用于识别多个半导体芯片中的至少一个位故障的方法，系统和程序产品。本发明的第一方面提供了一种识别多个半导体芯片中的至少一个位故障签名的方法，所述方法包括：对所述多个半导体芯片中的每个故障位进行计数故障; 确定故障位中最常见的故障位（MCFB）; 建立包括MCFB在内的位故障签名; 在MCFB故障的半导体芯片上的每个故障位的计数失败; 确定在MCFB故障的半导体芯片上的故障位中的下一个最常故障位（NMCFB）; 确定当MCFB发生故障时，NMCFB是否会失败; 并且响应于当MCFB失败时NMCFB趋向于失败的确定，将NMCFB添加到位故障签名。

3. 发明申请

US20100164013A1 RANDOM PERSONALIZATION OF CHIPS DURING FABRICATION 有权
标题翻译：制造期间随机个性化
公开(公告)号：US20100164013A1
公开(公告)日：2010-07-01
申请号：US12344725
申请日：2008-12-29
申请人： Mark D. Jaffe , Stephen A. Mongeon , Leah M.P. Pastel , Jed H. Rankin
发明人： Mark D. Jaffe , Stephen A. Mongeon , Leah M.P. Pastel , Jed H. Rankin
IPC分类号： H01L27/088 , H01L21/66 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/66 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc.
摘要翻译：公开了用于在制造期间随机个性化芯片的方法的实施例，个性化芯片结构和用于这种个性化芯片结构的设计结构。实施例使用电子设备设计和制造过程来随机地或伪随机地在每个芯片上形成的特定电子设备的一个或多个实例中创建特定变化。调整设备设计和制造过程，使得特定变化以某种预定概率发生，从而产生期望的硬件分布和个性化每个芯片。所得到的个性化芯片可用于芯片的模态分配。例如，当单芯片设计可用于支持多种应用时，芯片可以被个性化以允许排序。所产生的个性化芯片也可以用于随机数生成，用于创建唯一的片上标识符，私钥等。

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