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1. 发明申请

US20070287244A1 ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS 审中-公开
标题翻译： CMOS S / D SiGe工艺的替代整合方案
公开(公告)号：US20070287244A1
公开(公告)日：2007-12-13
申请号：US11739099
申请日：2007-04-24
申请人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
发明人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
IPC分类号： H01L21/8236
CPC分类号： H01L21/823814 , H01L21/823864
摘要： A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner. The method can also include implanting in the semiconductor substrate a source and drain region for the PMOS.
摘要翻译：一种用于在衬底上制造具有相邻PMOS和NMOS器件的半导体器件的方法包括在半导体衬底上形成具有PMOS硬掩模的PMOS栅电极，其间具有PMOS栅极介电层，在NMOS栅极上形成NMOS栅极半导体衬底，其间具有NMOS栅极介电层，在PMOS栅电极的一部分上方和NMOS栅电极的一部分之上形成氧化物衬垫，形成轻掺杂的N-Halo注入，在氧化物衬垫上沉积氮化物层以覆盖所述NMOS器件的图案沉积在所述半导体衬底上的光致抗蚀剂，从所述PMOS器件蚀刻所述氮化物层，其中所述蚀刻氮化物层离开所述氧化物衬底上的所述氮化物层的一部分，蚀刻半导体衬底以形成Si凹槽并且将SiGe沉积到Si凹部中，其中SiGe和氮化物层包围氧化物衬垫。该方法还可以包括在半导体衬底中注入用于PMOS的源极和漏极区域。

2. 发明申请

US20070284668A1 CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS 审中-公开
标题翻译： CMOS S / D SiGe器件与替代整合过程
公开(公告)号：US20070284668A1
公开(公告)日：2007-12-13
申请号：US11739103
申请日：2007-04-24
申请人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
发明人： Meihua Shen , Yonah Cho , Mark Kawaguchi , Faran Nouri , Diana Ma
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/28044 , H01L21/823807 , H01L29/165 , H01L29/518 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a substrate having regions filled with an additive that forms a source/drain for a MOS device, a gate dielectric layer deposited over the substrate, the gate dielectric layer electrically isolates the substrate from subsequently deposited layers, a gate electrode deposited over the gate dielectric layer, an oxide liner formed along laterally opposite sidewalls of the gate electrode, a nitride layer formed along the oxide liner extending above the gate electrode, and wherein the additive and the nitride layer enclose the gate electrode.
摘要翻译：半导体器件包括具有填充有添加剂的区域的衬底，其形成用于MOS器件的源极/漏极，沉积在衬底上的栅极电介质层，栅极介电层将衬底与随后沉积的层电隔离，栅极电极沉积在栅极电介质层，沿着栅电极的横向相对的侧壁形成的氧化物衬垫，沿着在栅电极上方延伸的氧化物衬垫形成的氮化物层，并且其中添加剂和氮化物层包围栅电极。

3. 发明授权

US08330225B2 NMOS transistor devices and methods for fabricating same 有权
标题翻译： NMOS晶体管器件及其制造方法
公开(公告)号：US08330225B2
公开(公告)日：2012-12-11
申请号：US13190957
申请日：2011-07-26
申请人： Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
发明人： Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
IPC分类号： H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636
摘要： NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.
摘要翻译：具有受控的通道应变和结电阻的NMOS晶体管及其制造方法在此提供。在一些实施例中，NMOS晶体管可以包括晶体管堆叠，其包括在p型硅区域上形成的栅极电介质和栅电极; 以及源极/漏极区域，其设置在晶体管堆叠的两侧并且在晶体管堆叠之间和之下限定沟道区域，源极漏极区域包括具有晶格调节元件的第一硅层和具有晶格堆叠的一个或多个第二硅层调整元件和设置在第一硅层顶上的n型掺杂剂。

4. 发明申请

US20110278651A1 NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME 有权
标题翻译： NMOS晶体管器件及其制造方法
公开(公告)号：US20110278651A1
公开(公告)日：2011-11-17
申请号：US13190957
申请日：2011-07-26
申请人： Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
发明人： Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636
摘要： NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer.
摘要翻译：具有受控的通道应变和结电阻的NMOS晶体管及其制造方法在此提供。在一些实施例中，NMOS晶体管可以包括晶体管堆叠，其包括在p型硅区域上形成的栅极电介质和栅电极; 以及源极/漏极区域，其设置在晶体管堆叠的两侧并且在晶体管堆叠之间和之下限定沟道区域，源极漏极区域包括具有晶格调节元件的第一硅层和具有晶格堆叠的一个或多个第二硅层调整元件和设置在第一硅层顶上的n型掺杂剂。

5. 发明授权

US07994015B2 NMOS transistor devices and methods for fabricating same 有权
标题翻译： NMOS晶体管器件及其制造方法
公开(公告)号：US07994015B2
公开(公告)日：2011-08-09
申请号：US12763403
申请日：2010-04-20
申请人： Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
发明人： Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636
摘要： NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.
摘要翻译：具有受控的通道应变和结电阻的NMOS晶体管及其制造方法在此提供。在一些实施例中，用于形成NMOS晶体管的方法可以包括提供具有p型硅区域和设置在其上的栅极堆叠的衬底，栅极堆叠部分地限定源极和漏极区域; 在所述源极和漏极区内沉积具有晶格调节元件的未掺杂的第一硅层，所述第一硅层位于所述p型硅区域的顶部; 以及在未掺杂的第一硅层的顶部沉积具有晶格调节元件和n型掺杂剂的第二硅层。

6. 发明授权

US06274445B1 Method of manufacturing shallow source/drain junctions in a salicide process 失效
标题翻译：在自杀过程中制造浅源/排水路的方法
公开(公告)号：US06274445B1
公开(公告)日：2001-08-14
申请号：US09243739
申请日：1999-02-03
申请人： Faran Nouri
发明人： Faran Nouri
IPC分类号： H01L21336
CPC分类号： H01L29/41783 , H01L21/2652 , H01L29/665 , H01L29/66545
摘要： An ion implanting process allows for shallow source and drain junctions of the transistor. According to one example embodiment, a BARC layer is formed over a gate, and a poly-crystalline or amorphous silicon shield is deposited over the source and drain regions, then the BARC and silicon are chemically mechanically polished. The poly-crystalline or amorphous silicon shield absorbs the initial impact the dopant species of ion implantation and reduces the incidence of irreversible source/drain crystal damage caused by the process. After the ion implantation, the species implanted in the poly or amorphous silicon is diffused into the source/drain regions by annealing. An additional siliciding of the poly or amorphous silicon covering the source and drain minimizes the need for deeper source/drain junctions and hence improves short-channel properties.
摘要翻译：离子注入工艺允许晶体管的浅源极和漏极结。根据一个示例实施例，在栅极上形成BARC层，并且多晶硅或非晶硅屏蔽层沉积在源区和漏区上，则BARC和硅经化学机械抛光。多晶硅或非晶硅屏蔽吸收离子注入的掺杂物质的初始影响，并减少由该过程引起的不可逆源/漏晶体损伤的发生。离子注入后，通过退火将注入在多晶硅或非晶硅中的物质扩散到源/漏区。覆盖源极和漏极的多晶硅或非晶硅的另外的硅化将对更深的源极/漏极结的需要最小化，从而改善了短沟道特性。

7. 发明授权

US08105908B2 Methods for forming a transistor and modulating channel stress 有权
标题翻译：形成晶体管和调制沟道应力的方法
公开(公告)号：US08105908B2
公开(公告)日：2012-01-31
申请号：US11165282
申请日：2005-06-23
申请人： Sunderraj Thirupapuliyur , Faran Nouri , Lori Washington
发明人： Sunderraj Thirupapuliyur , Faran Nouri , Lori Washington
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： Methods are provided for manufacturing transistors and altering the stress in the channel region of a single transistor. One or more parameters that are effect stress in the channel region are altered for a single transistor to increase or decrease the channel stress in PMOS and NMOS transistors.
摘要翻译：提供了用于制造晶体管并改变单个晶体管的沟道区域中的应力的方法。对于单个晶体管，在沟道区域中影响应力的一个或多个参数被改变以增加或减小PMOS和NMOS晶体管中的沟道应力。

8. 发明授权

US07968413B2 Methods for forming a transistor 有权
标题翻译：形成晶体管的方法
公开(公告)号：US07968413B2
公开(公告)日：2011-06-28
申请号：US12176274
申请日：2008-07-18
申请人： Faran Nouri , Lori D. Washington , Victor Moroz
发明人： Faran Nouri , Lori D. Washington , Victor Moroz
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.
摘要翻译：提供了用于在诸如金属氧化物晶体管的衬底上形成半导体器件中沉积材料的方法。在一个实施例中，本发明通常提供一种处理衬底的方法，包括在具有第一导电性的衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅极的横向相对的侧壁上形成第一对侧壁间隔物在电极的相对侧蚀刻一对源/漏区定义，在源/漏区定义中选择性地沉积硅 - 锗材料，以及在沉积的硅 - 锗材料中注入掺杂剂以形成源极/漏极区域具有第二导电性。

9. 发明申请

US20070298575A1 METHODS FOR CONTACT RESISTANCE REDUCTION OF ADVANCED CMOS DEVICES 有权
标题翻译：接触电阻降低高级CMOS器件的方法
公开(公告)号：US20070298575A1
公开(公告)日：2007-12-27
申请号：US11426135
申请日：2006-06-23
申请人： Faran Nouri , Eun-Ha Kim , Sunderraj Thirupapuliyur , Vijay Parihar
发明人： Faran Nouri , Eun-Ha Kim , Sunderraj Thirupapuliyur , Vijay Parihar
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L21/26513 , H01L21/268 , H01L21/823814 , H01L21/823835 , H01L29/6659 , H01L29/7833
摘要： Methods for reducing contact resistance in semiconductor devices are provided in the present invention. In one embodiment, the method includes providing a substrate having semiconductor device formed thereon, wherein the device has source and drain regions and a gate structure formed therein, performing a silicidation process on the substrate by a thermal annealing process, and performing a laser anneal process on the substrate. In another embodiment, the method includes providing a substrate having implanted dopants, performing a silicidation process on the substrate by a thermal annealing process, and activating the dopants by a laser anneal process.
摘要翻译：在本发明中提供了用于降低半导体器件中的接触电阻的方法。在一个实施例中，该方法包括提供其上形成有半导体器件的衬底，其中器件具有形成于其中的源极和漏极区域以及栅极结构，通过热退火工艺在衬底上进行硅化处理，并且执行激光退火工艺在基板上。在另一个实施方案中，该方法包括提供具有注入的掺杂剂的衬底，通过热退火工艺在衬底上进行硅化处理，以及通过激光退火工艺激活掺杂剂。

10. 发明申请

US20050287752A1 Methods for forming a transistor 有权
标题翻译：形成晶体管的方法
公开(公告)号：US20050287752A1
公开(公告)日：2005-12-29
申请号：US11123588
申请日：2005-05-06
申请人： Faran Nouri , Lori Washington , Victor Moroz
发明人： Faran Nouri , Lori Washington , Victor Moroz
IPC分类号： H01L21/336 , H01L29/165
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/7848
摘要： Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.
摘要翻译：提供了用于在诸如金属氧化物晶体管的衬底上形成半导体器件中沉积材料的方法。在一个实施例中，本发明通常提供一种处理衬底的方法，包括在具有第一导电性的衬底上形成栅极电介质，在栅极电介质上形成栅电极，在栅极的横向相对的侧壁上形成第一对侧壁间隔物在电极的相对侧蚀刻一对源/漏区定义，在源/漏区定义中选择性地沉积硅 - 锗材料，以及在沉积的硅 - 锗材料中注入掺杂剂以形成源极/漏极区域具有第二导电性。

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