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1. 发明授权

US07514348B2 Sidewall coverage for copper damascene filling 有权
标题翻译：铜镶嵌填料的侧壁覆盖
公开(公告)号：US07514348B2
公开(公告)日：2009-04-07
申请号：US11860639
申请日：2007-09-25
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L21/302
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.
摘要翻译：描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。具体应用是用铜填充沟槽以形成镶嵌线。首先，通过PVD将种子层沉积在孔或沟槽中。然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

2. 发明授权

US06686280B1 Sidewall coverage for copper damascene filling 有权
公开(公告)号：US06686280B1
公开(公告)日：2004-02-03
申请号：US09989802
申请日：2001-11-20
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L2100
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

3. 发明授权

US07282450B2 Sidewall coverage for copper damascene filling 有权
标题翻译：铜镶嵌填料的侧壁覆盖
公开(公告)号：US07282450B2
公开(公告)日：2007-10-16
申请号：US10733722
申请日：2003-12-11
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.
摘要翻译：描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。具体应用是用铜填充沟槽以形成镶嵌线。首先，通过PVD将种子层沉积在孔或沟槽中。然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

4. 发明授权

US06242338B1 Method of passivating a metal line prior to deposition of a fluorinated silica glass layer 有权
标题翻译：在沉积氟化石英玻璃层之前钝化金属线的方法
公开(公告)号：US06242338B1
公开(公告)日：2001-06-05
申请号：US09422175
申请日：1999-10-22
申请人： Chung-Shi Liu , Shau-Lin Shue , Yao-yi Cheng , Chen-Hua Yu , Mei-Yun Wang
发明人： Chung-Shi Liu , Shau-Lin Shue , Yao-yi Cheng , Chen-Hua Yu , Mei-Yun Wang
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/02274 , H01L21/02304 , H01L21/31629 , H01L21/321 , H01L21/76832 , H01L21/76834 , H01L21/76888
摘要： A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.
摘要翻译：已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

5. 发明申请

US20080009133A1 Sidewall Coverage For Copper Damascene Filling 有权
标题翻译：铜镶嵌填料的侧壁覆盖
公开(公告)号：US20080009133A1
公开(公告)日：2008-01-10
申请号：US11860639
申请日：2007-09-25
申请人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
发明人： Shau-Lin Shue , Mei-Yun Wang , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76862 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L2221/1089
摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.
摘要翻译：描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。具体应用是用铜填充沟槽以形成镶嵌线。首先，通过PVD将种子层沉积在孔或沟槽中。然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

6. 发明授权

US6096651A Key-hole reduction during tungsten plug formation 有权
标题翻译：钨丝塞形成期间的关键孔减少
公开(公告)号：US6096651A
公开(公告)日：2000-08-01
申请号：US228126
申请日：1999-01-11
申请人： Mei-Yun Wang , Chen-Hua Yu , Shau-Lin Shue
发明人： Mei-Yun Wang , Chen-Hua Yu , Shau-Lin Shue
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76865 , H01L21/76804 , H01L21/76843 , H01L21/76862
摘要： The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.
摘要翻译：通过在阻挡层就位之后的氩气中的软溅射，克服了在小直径通孔填充期间形成孔洞的问题。该溅射步骤可以使用两次一次来加宽新形成的通孔的口，并且在阻挡层就位之后的第二次，从而进一步扩大口（以及从阻挡层的表面去除氧化物））。在替代的可选实施例中，通孔口的加宽可以在阻挡层被铺设之后被限制到单个溅射步骤。在任一种情况下，随后填充通孔而没有任何键孔形成。

7. 发明授权

US07205234B2 Method of forming metal silicide 有权
标题翻译：形成金属硅化物的方法
公开(公告)号：US07205234B2
公开(公告)日：2007-04-17
申请号：US10772938
申请日：2004-02-05
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.
摘要翻译：已经开发了在MOSFET结构的区域上优化硅化镍的形成的方法。该方法的特征是使用在低于该温度的镍硅化物不稳定性和聚集发生的温度下进行的退火程序形成硅化镍。首先在镍沉积之前在MOSFET结构上形成薄的钛中间层，允许在镍沉积之后进行的退火程序在约400℃的温度下成功形成硅化镍。为了获得所需的共形性和厚度均匀性，薄的通过原子层沉积工艺形成钛夹层。

8. 发明申请

US20050272235A1 Method of forming silicided gate structure 失效
标题翻译：形成硅化栅结构的方法
公开(公告)号：US20050272235A1
公开(公告)日：2005-12-08
申请号：US10859730
申请日：2004-06-03
申请人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/4763 , H01L29/49
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/66507 , H01L29/785
摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.
摘要翻译：提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

9. 发明申请

US20050092598A1 Sputtering process with temperature control for salicide application 审中-公开
标题翻译：用于自杀剂应用的温度控制的溅射过程
公开(公告)号：US20050092598A1
公开(公告)日：2005-05-05
申请号：US10702970
申请日：2003-11-05
申请人： Mei-Yun Wang , Chih-Wei Chang , Chii-Ming Wu , Cheng-Tung Lin , Shau-Lin Shue
发明人： Mei-Yun Wang , Chih-Wei Chang , Chii-Ming Wu , Cheng-Tung Lin , Shau-Lin Shue
IPC分类号： C23C14/16 , H01L21/285 , C23C16/00 , C23C14/32
CPC分类号： H01L21/28518 , C23C14/16
摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.
摘要翻译：一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

10. 发明授权

US06531389B1 Method for forming incompletely landed via with attenuated contact resistance 有权
标题翻译：通过减弱接触电阻形成不完全着陆通孔的方法
公开(公告)号：US06531389B1
公开(公告)日：2003-03-11
申请号：US09467130
申请日：1999-12-20
申请人： Shau-Lin Shue , Mei-Yun Wang
发明人： Shau-Lin Shue , Mei-Yun Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/76802 , Y10S438/958
摘要： A method for forming a via through a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer exposed within the purged via while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer. Incident to employing the purging of the via to form the purged via and the plasma passivating of the purged via to form the plasma passivated purged via, the conductor stud layer when formed into the plasma passivated purged via is formed with attenuated contact resistance with respect to the plasma passivated patterned conductor layer.
摘要翻译：一种通过电介质层形成通孔的方法。首先提供基板。然后在衬底上形成图案化的导体层。然后形成覆盖图案化导体层的电介质层。然后通过电介质层形成通孔以访问图案化的导体层，其中通孔不完全地着落在图案化的导体层上。然后在使用真空吹扫方法的同时吹扫通孔以形成清洗的通孔。然后钝化净化的通孔并钝化暴露在清洗过的通孔内的图案化导体层，同时采用等离子体钝化方法形成等离子体钝化清洗的通孔和等离子体钝化的图案化导体层。最后，然后形成通过导体柱层被钝化的等离子体钝化。为了采用清洗通孔以形成清洗过的通孔和被清除通孔的等离子体钝化以形成等离子体钝化净化通孔的事件，当形成等离子体钝化净化过的通孔时，导体柱层形成相对于等离子体钝化图案化导体层。

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