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1. 发明授权

US06521539B1 Selective etch method for selectively etching a multi-layer stack layer 有权
标题翻译：用于选择性蚀刻多层堆叠层的选择性蚀刻方法
公开(公告)号：US06521539B1
公开(公告)日：2003-02-18
申请号：US09303837
申请日：1999-05-03
申请人： Mei Sheng Zhou , Xue Chun Dai , Chiew Wah Yap
发明人： Mei Sheng Zhou , Xue Chun Dai , Chiew Wah Yap
IPC分类号： H01L21302
CPC分类号： H01L29/66545 , H01L21/31116 , H01L21/31138
摘要： A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer. There is then etched selectively, while employing a first etch method which employs the first etchant, the third upper patterned microelectronic layer while the first lower microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer are encapsulated with the encapsulating layer. Finally, there is then stripped, while employing a second etch method which employs a second etchant, from the first microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer the encapsulating layer. The method may be employed for stripping from a gate electrode within a field effect transistor (FET) a patterned dielectric cap layer formed upon the gate electrode while not etching a gate dielectric layer upon Which is formed the gate electrode within the field effect transistor (FET).
摘要翻译：一种用于形成图案化微电子层的方法。首先提供基板。然后在衬底上形成多层堆叠层，其包括：（1）第一下部微电子层; （2）形成在第一下部微电子层上的第二中间图案化微电子层; 和（3）在第二中间图案化微电子层上形成的第三上图形微电子层，其中第一下微电子层和第三上图形微电子层易于在第一蚀刻剂内蚀刻。然后形成封装第一下部微电子层和第二中间图案化微电子层的至少部分，同时将第三上部图案化微电子层的至少一部分暴露于封装层。然后选择性地蚀刻，同时使用采用第一蚀刻剂的第一蚀刻方法，第三上图案化微电子层，而第一下微电子层和第二中间图案化微电子层的至少部分用封装层封装。最后，然后剥离，同时采用采用第二蚀刻剂的第二蚀刻方法，从第一微电子层和第二中间图案化微电子层的至少部分封装层。该方法可用于从场效应晶体管（FET）内的栅电极剥离形成在栅电极上的图案化电介质盖层，同时不蚀刻在场效应晶体管（FET）内形成栅电极的栅极电介质层）。

2. 发明授权

US08394724B2 Processing with reduced line end shortening ratio 有权
标题翻译：处理缩短了线端缩短率
公开(公告)号：US08394724B2
公开(公告)日：2013-03-12
申请号：US11843629
申请日：2007-08-22
申请人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
发明人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
IPC分类号： H01L21/312
CPC分类号： H01L21/32137 , H01L21/32139
摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
摘要翻译：用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

3. 发明授权

US08324011B2 Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing 有权
标题翻译：实现温度相关的开关层，以提高退火过程中的温度均匀性
公开(公告)号：US08324011B2
公开(公告)日：2012-12-04
申请号：US11853156
申请日：2007-09-11
申请人： Chyiu Hyia Poon , Alex See , Mei Sheng Zhou
发明人： Chyiu Hyia Poon , Alex See , Mei Sheng Zhou
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/268
摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.
摘要翻译：本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。结果，半导体在晶片上以一致的温度退火。温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

4. 发明申请

US20110281410A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME 有权
标题翻译：用于制造具有外延通道的半导体器件和具有其的晶体管的方法
公开(公告)号：US20110281410A1
公开(公告)日：2011-11-17
申请号：US13190805
申请日：2011-07-26
申请人： JINPING LIU , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
发明人： JINPING LIU , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

5. 发明授权

US08012839B2 Method for fabricating a semiconductor device having an epitaxial channel and transistor having same 有权
标题翻译：用于制造具有外延沟道的半导体器件的方法和具有其的晶体管
公开(公告)号：US08012839B2
公开(公告)日：2011-09-06
申请号：US12040562
申请日：2008-02-29
申请人： Jinping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

6. 发明授权

US07966142B2 Multi-variable regression for metrology 有权
标题翻译：计量学的多元回归
公开(公告)号：US07966142B2
公开(公告)日：2011-06-21
申请号：US12103690
申请日：2008-04-15
申请人： Wen Zhan Zhou , Zheng Zou , Jasper Goh , Mei Sheng Zhou
发明人： Wen Zhan Zhou , Zheng Zou , Jasper Goh , Mei Sheng Zhou
IPC分类号： G01D21/00 , G06F19/00
CPC分类号： H01L22/12 , G01B21/045 , G01B2210/56 , H01L22/20
摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.
摘要翻译：描述了一种评估测量工具精度的方法。多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。然后执行多变量回归以为数据集生成最佳拟合平面。测定系数（R2值）表示MTUT的精度指标。

7. 发明授权

US07776699B2 Strained channel transistor structure and method 有权
标题翻译：应变通道晶体管结构和方法
公开(公告)号：US07776699B2
公开(公告)日：2010-08-17
申请号：US12025788
申请日：2008-02-05
申请人： Jin Ping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jin Ping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/778
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/165 , H01L29/66636
摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
摘要翻译：一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变底物。

8. 发明申请

US20090218597A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME 有权
标题翻译：用于制造具有外延通道的半导体器件和具有其的晶体管的方法
公开(公告)号：US20090218597A1
公开(公告)日：2009-09-03
申请号：US12040562
申请日：2008-02-29
申请人： Jinping Liu , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

9. 发明申请

US20090053864A1 METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING HETEROGENEOUS CRYSTALLINE ORIENTATIONS 审中-公开
标题翻译：用于制备具有异质结晶取向的半导体结构的方法
公开(公告)号：US20090053864A1
公开(公告)日：2009-02-26
申请号：US11844074
申请日：2007-08-23
申请人： Jinping Liu , Alex K.H. See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Alex K.H. See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/02381 , H01L21/02387 , H01L21/02395 , H01L21/02433 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02538 , H01L21/02546 , H01L21/02609 , H01L29/045
摘要： A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from the crystalline orientation of a semiconductor region underlying the buffer. The method also includes fabricating a semiconductor structure having a p-type device region and an n-type device region, where a supporting semiconductor substrate is either n-type or p-type and where the semiconductor material is separated from the substrate by a buffer and has a crystalline orientation that differs from the crystalline orientation of the substrate.
摘要翻译：一种通过使用覆盖在半导体衬底上的外延缓冲层形成包含具有指定结晶取向的半导体材料的区域来制造具有异质结晶取向的半导体结构的方法。缓冲器提供转移体，使得半导体材料具有不同于缓冲器下面的半导体区域的晶体取向的结晶取向。该方法还包括制造具有p型器件区域和n型器件区域的半导体结构，其中支持半导体衬底是n型或p型，并且半导体材料通过缓冲器与衬底分离并且具有不同于衬底的晶体取向的结晶取向。

10. 发明授权

US06987321B2 Copper diffusion deterrent interface 失效
标题翻译：铜扩散阻止界面
公开(公告)号：US06987321B2
公开(公告)日：2006-01-17
申请号：US10718865
申请日：2003-11-21
申请人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subbash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
发明人： Simon Chooi , Yakub Aliyu , Mei Sheng Zhou , John Leonard Sudijono , Subbash Gupta , Sudipto Ranendra Roy , Paul Kwok Keung Ho , Yi Xu
IPC分类号： H01L23/48
CPC分类号： H01L21/76844 , H01L21/28556 , H01L21/31111 , H01L21/314 , H01L21/76807
摘要： Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
摘要翻译：用于形成双镶嵌互连结构的方法和产品，其中将铜硫化物界面层作为开口的侧壁沉积阻止铜离子迁移或扩散到电介质材料中。

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