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1. 发明申请

US20080032513A1 INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY 有权
标题翻译：集成电路系统，包括氮化层技术
公开(公告)号：US20080032513A1
公开(公告)日：2008-02-07
申请号：US11428618
申请日：2006-07-05
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种集成电路系统，包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

2. 发明授权

US06632745B1 Method of forming almost L-shaped spacer for improved ILD gap fill 有权
标题翻译：形成几乎L型间隔物以改善ILD间隙填充的方法
公开(公告)号：US06632745B1
公开(公告)日：2003-10-14
申请号：US10222387
申请日：2002-08-16
申请人： Chiew Wah Yap , Zheng Zou , Eng Hua Lim , Nguyen Lac , Yelehanka Pradeep , Manni Lal
发明人： Chiew Wah Yap , Zheng Zou , Eng Hua Lim , Nguyen Lac , Yelehanka Pradeep , Manni Lal
IPC分类号： H01L21311
CPC分类号： H01L29/6653 , H01L29/665
摘要： A patterned and etched layer of gate electrode material is formed over the active surface of a substrate, a layer of liner oxide is created, gate spacers are created. Under the first embodiment of the invention, a layer of TEOS is deposited over the created structure over which a layer of nitride is deposited, The layer of nitride is etched, this etch is extended into an overetch creating openings through the layer of TEOS where this layer overlies the gate spacers. The gate spacers are then further etched. Under the second embodiment of the invention, a layer of TEOS is deposited over the created structure. The layer of TEOS is etched, stopping on the silicon nitride of the gate spacers. The gate spacers are then further etched.
摘要翻译：在衬底的有源表面上形成图案化和蚀刻的栅极材料层，形成衬垫氧化物层，形成栅极间隔物。在本发明的第一个实施方案中，存在一层TEOS 在其上沉积氮化物层的所产生的结构上。蚀刻氮化物层，该蚀刻扩展到通过TEOS层产生开口的过蚀刻，其中该层覆盖在栅极间隔物上。然后进一步蚀刻栅极间隔物。在本发明的第二实施例中，在所创建的结构上沉积TEOS层。蚀刻TEOS层，停留在栅极间隔物的氮化硅上。然后进一步蚀刻栅极间隔物

3. 发明授权

US06294480B1 Method for forming an L-shaped spacer with a disposable organic top coating 有权
标题翻译：用一次性有机顶涂层形成L形间隔物的方法
公开(公告)号：US06294480B1
公开(公告)日：2001-09-25
申请号：US09443427
申请日：1999-11-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jie Yu , Minghui Fan , Chiew Wah Yap
发明人： Yelehanka Ramachandramurthy Pradeep , Jie Yu , Minghui Fan , Chiew Wah Yap
IPC分类号： H01L2131
CPC分类号： H01L29/6653 , H01L21/31116 , H01L21/31144 , H01L29/6659
摘要： A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.
摘要翻译：一种使用牺牲有机顶涂层形成L形间隔件的方法。提供其上具有栅极结构的半导体结构。在栅极结构上形成衬里氧化物层。介电间隔层形成在衬垫氧化物层上。在优选实施例中，电介质间隔层包括氮化硅层或氮氧化硅层。在电介质间隔层上形成牺牲有机层。牺牲有机层和电介质间隔层被各向异性蚀刻以形成包括三角形牺牲有机结构和L形介电间隔物的间隔物。去除三角形牺牲有机结构留下L形介电隔离物。

4. 发明申请

US20130034954A1 INTEGRATED CIRCUIT SYSTEM INCLUDING NITRIDE LAYER TECHNOLOGY 审中-公开
标题翻译：集成电路系统，包括氮化层技术
公开(公告)号：US20130034954A1
公开(公告)日：2013-02-07
申请号：US13647339
申请日：2012-10-08
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/283
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种用于制造集成电路系统的集成电路方法，该集成电路系统包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

5. 发明授权

US08283263B2 Integrated circuit system including nitride layer technology 有权
标题翻译：集成电路系统包括氮化层技术
公开(公告)号：US08283263B2
公开(公告)日：2012-10-09
申请号：US11428618
申请日：2006-07-05
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/469
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种用于制造集成电路系统的集成电路方法，该集成电路系统包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

6. 发明授权

US06521539B1 Selective etch method for selectively etching a multi-layer stack layer 有权
标题翻译：用于选择性蚀刻多层堆叠层的选择性蚀刻方法
公开(公告)号：US06521539B1
公开(公告)日：2003-02-18
申请号：US09303837
申请日：1999-05-03
申请人： Mei Sheng Zhou , Xue Chun Dai , Chiew Wah Yap
发明人： Mei Sheng Zhou , Xue Chun Dai , Chiew Wah Yap
IPC分类号： H01L21302
CPC分类号： H01L29/66545 , H01L21/31116 , H01L21/31138
摘要： A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer. There is then etched selectively, while employing a first etch method which employs the first etchant, the third upper patterned microelectronic layer while the first lower microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer are encapsulated with the encapsulating layer. Finally, there is then stripped, while employing a second etch method which employs a second etchant, from the first microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer the encapsulating layer. The method may be employed for stripping from a gate electrode within a field effect transistor (FET) a patterned dielectric cap layer formed upon the gate electrode while not etching a gate dielectric layer upon Which is formed the gate electrode within the field effect transistor (FET).
摘要翻译：一种用于形成图案化微电子层的方法。首先提供基板。然后在衬底上形成多层堆叠层，其包括：（1）第一下部微电子层; （2）形成在第一下部微电子层上的第二中间图案化微电子层; 和（3）在第二中间图案化微电子层上形成的第三上图形微电子层，其中第一下微电子层和第三上图形微电子层易于在第一蚀刻剂内蚀刻。然后形成封装第一下部微电子层和第二中间图案化微电子层的至少部分，同时将第三上部图案化微电子层的至少一部分暴露于封装层。然后选择性地蚀刻，同时使用采用第一蚀刻剂的第一蚀刻方法，第三上图案化微电子层，而第一下微电子层和第二中间图案化微电子层的至少部分用封装层封装。最后，然后剥离，同时采用采用第二蚀刻剂的第二蚀刻方法，从第一微电子层和第二中间图案化微电子层的至少部分封装层。该方法可用于从场效应晶体管（FET）内的栅电极剥离形成在栅电极上的图案化电介质盖层，同时不蚀刻在场效应晶体管（FET）内形成栅电极的栅极电介质层）。

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