会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明授权
    • Methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis
    • 用于测量衬底特性或制备用于分析的衬底的方法和系统
    • US07365321B2
    • 2008-04-29
    • US11086048
    • 2005-03-22
    • Mehran Nasser-GhodsiMark Borowicz
    • Mehran Nasser-GhodsiMark Borowicz
    • H01J37/06
    • H01J37/317G01N1/32H01J37/244H01J37/3005H01J2237/2814H01J2237/3174H01J2237/31745
    • Methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis are provided. One method for measuring a characteristic of a substrate includes removing a portion of a feature on the substrate using an electron beam to expose a cross-sectional profile of a remaining portion of the feature. The feature may be a photoresist feature. The method also includes measuring a characteristic of the cross-sectional profile. A method for preparing a substrate for analysis includes removing a portion of a material on the substrate proximate to a defect using chemical etching in combination with an electron beam. The defect may be a subsurface defect or a partially subsurface defect. Another method for preparing a substrate for analysis includes removing a portion of a material on a substrate proximate to a defect using chemical etching in combination with an electron beam and a light beam.
    • 提供了用于测量基板的特性或准备用于分析的基板的方法和系统。 用于测量衬底的特性的一种方法包括使用电子束去除衬底上的特征的一部分以暴露特征的剩余部分的横截面轮廓。 该特征可以是光致抗蚀剂特征。 该方法还包括测量横截面轮廓的特性。 制备用于分析的基板的方法包括使用化学蚀刻与电子束结合来去除靠近缺陷的衬底上的材料的一部分。 缺陷可能是地下缺陷或部分地下缺陷。 制备用于分析的衬底的另一种方法包括使用化学蚀刻与电子束和光束组合地去除邻近缺陷的衬底上的材料的一部分。
    • 7. 发明授权
    • Electron generation and delivery system for contamination sensitive emitters
    • 用于污染敏感发射器的电子发射和传输系统
    • US08530867B1
    • 2013-09-10
    • US13457897
    • 2012-04-27
    • Mehran Nasser-Ghodsi
    • Mehran Nasser-Ghodsi
    • H01J37/073
    • H01J37/073H01J37/265H01J2237/022H01J2237/06341H01J2237/0653
    • Contamination may be removed from a field emitter unit during operation of the emitter unit in an environment at a pressure that lies within a range between 10−6 torr and 10−8 torr. At regular predetermined intervals an electron beam from an emitter tip may be deflected away from a path through a beam defining aperture and onto an electron collector. An electron beam current to the electron collector may be determined and the emitter unit may be flash heated if the current to the electron collector is below a threshold. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    • 在位于10-6托和10-8托之间的压力的环境中,在发射器单元操作期间,可以从场发射器单元去除污染物。 以规则的预定间隔,来自发射极尖端的电子束可以偏离通过光束限定孔径并且到电子收集器的路径。 可以确定到电子收集器的电子束电流,并且如果到电子收集器的电流低于阈值,则发射器单元可以被闪光加热。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。
    • 9. 发明授权
    • Calibration standard for a dual beam (FIB/SEM) machine
    • 双光束(FIB / SEM)机器的校准标准
    • US07576317B1
    • 2009-08-18
    • US12116890
    • 2008-05-07
    • Marco TortoneseMehran Nasser-Ghodsi
    • Marco TortoneseMehran Nasser-Ghodsi
    • G01N21/84
    • H01J40/14
    • Calibration of measurements of features made with a system having a micromachining tool and an analytical tool is disclosed. The measurements can be calibrated with a standard having a calibrated feature with one or more known dimensions. The standard may have one or more layers including a single crystal layer. The calibrated feature may include one or more vertical features characterized by one or more known dimensions and formed through the single crystal layer. A trench is formed in a sample with the micromachining tool to reveal a sample feature. The analytical tool measures one or more dimensions of the sample feature corresponding to one or more known dimensions of the calibrated feature. The known dimensions of the calibrated feature are measured with the same analytical tool. The measured dimensions of the sample feature and the calibrated feature can then be compared to the known dimensions of the calibrated feature.
    • 公开了使用具有微加工工具和分析工具的系统进行的特征的测量的校准。 测量可以用具有一个或多个已知尺寸的校准特征的标准进行校准。 标准可以具有包括单晶层的一层或多层。 经校准的特征可以包括由一个或多个已知尺寸表征并且通过单晶层形成的一个或多个垂直特征。 在微加工工具的样品中形成沟槽以露出样品特征。 分析工具测量与校准特征的一个或多个已知尺寸对应的样本特征的一个或多个维度。 使用相同的分析工具测量校准特征的已知尺寸。 然后将样本特征和校准特征的测量尺寸与已校准特征的已知尺寸进行比较。
    • 10. 发明申请
    • TUNGSTEN PLUG DEPOSITION QUALITY EVALUATION METHOD BY EBACE TECHNOLOGY
    • EBACE技术的TUNGSTEN PLUG沉积质量评估方法
    • US20090010526A1
    • 2009-01-08
    • US11622793
    • 2007-01-12
    • Yehiel GotkisSergey LopatinMehran Nasser-Ghodsi
    • Yehiel GotkisSergey LopatinMehran Nasser-Ghodsi
    • G06K9/00G01R31/26H01L23/58
    • H01L22/12H01L22/34
    • A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.
    • 本发明的第一实施例涉及一种用于评估集成电路晶片上的结构质量的方法。 在集成的或在测试晶片上形成的测试结构暴露于电子束和电子束激活的化学蚀刻。 电子束活化的蚀刻气体或蒸气蚀刻测试结构,其在蚀刻后分析以确定测试结构的质量的度量。 可以在统计过程控制中使用质量测量来调整用于在集成电路晶片上形成器件结构的参数。 测试结构形成在具有两个或更多个管芯的集成电路晶片上。 每个管芯具有一个或多个集成电路结构。 测试结构形成在两个或更多相邻模具之间的划线上。 每个测试结构可以在尺寸和/或组成上与一个或多个集成电路结构相对应。