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1. 发明申请

US20070055825A1 Managing coherence via put/get windows 失效
标题翻译：通过put / get窗口管理一致性
公开(公告)号：US20070055825A1
公开(公告)日：2007-03-08
申请号：US10468995
申请日：2002-02-25
申请人： Matthias Blumrich , Dong Chan , Paul Coteus , Alan Gata , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias Blumrich , Dong Chan , Paul Coteus , Alan Gata , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F13/28
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

2. 发明申请

US20070204112A1 LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
标题翻译：低延迟存储器访问和同步
公开(公告)号：US20070204112A1
公开(公告)日：2007-08-30
申请号：US11617276
申请日：2006-12-28
申请人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/52 , G06F2212/6028
摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
摘要翻译：与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。还公开了用于非连续数据结构的简单预取。重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测算法。这使得硬件能够有效地预取不连续但重复的存储器访问模式。

3. 发明申请

US20060248370A1 Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
标题翻译：使用多节点计算机故障隔离交换误差检测值的方法和装置
公开(公告)号：US20060248370A1
公开(公告)日：2006-11-02
申请号：US11106069
申请日：2005-04-14
申请人： Gheorghe Almasi , Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Sarabjeet Singh , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Gheorghe Almasi , Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Sarabjeet Singh , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F11/00
CPC分类号： G06F11/1633
摘要： The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created; the node fault detection apparatus retrieves them and stores them in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in commutative error detection values indicate that the node may be faulty.
摘要翻译：本发明涉及在多节点计算系统中使用交换性错误检测值（例如校验和）识别和隔离故障节点来执行故障隔离的方法和装置。在本发明中，形成多节点计算系统的节点被联网在一起，并且在程序执行期间通过网络传送信息彼此通信。当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值并将其存储在与节点相关联的交换错误检测装置中。间歇地，与多节点计算机系统相关联的节点故障检测装置检索保存在与节点相关联的交换性错误检测装置中的交换性错误检测值，并将其存储在存储器中。当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值; 节点故障检测装置检索它们并将其存储在存储器中。节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。交换性错误检测值的差异表明节点可能有故障。

4. 发明申请

US20080091842A1 OPTIMIZED SCALABLE NETWORK SWITCH 失效
标题翻译：优化可调网络交换机
公开(公告)号：US20080091842A1
公开(公告)日：2008-04-17
申请号：US11868223
申请日：2007-10-05
申请人： Matthias Blumrich , Dong Chen , Paul Coteus
发明人： Matthias Blumrich , Dong Chen , Paul Coteus
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2 m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.
摘要翻译：在具有多维配置的多个节点的大规模并行计算系统中，每个节点包括计算设备，用于将分组路由到其目的地节点的方法，包括生成2m个紧凑位中的至少一个包含从下游节点导出的信息的向量。存储在紧凑向量中的下行信息（诸如链路状态信息和下游缓冲器的丰满度）的多级仲裁过程被用于确定分组传输的优选方向和虚拟信道。优选的方向范围被编码，并且通过检查多个紧凑比特向量来选择虚拟信道。这种动态路由方法消除了路由表的必要性，从而增强了交换机的可扩展性。

5. 发明授权

US07383490B2 Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
标题翻译：使用多节点计算机故障隔离交换误差检测值的方法和装置
公开(公告)号：US07383490B2
公开(公告)日：2008-06-03
申请号：US11106069
申请日：2005-04-14
申请人： Gheorghe Almasi , Matthias Augustin Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Sarabjeet Singh , Burkhard D. Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Gheorghe Almasi , Matthias Augustin Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Sarabjeet Singh , Burkhard D. Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1633
摘要： Methods and apparatus perform fault isolation in multiple node computing systems using commutative error detection values for—example, checksums—to identify and to isolate faulty nodes. When information associated with a reproducible portion of a computer program is injected into a network by a node, a commutative error detection value is calculated. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created and stored in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in values indicate a possible faulty node.
摘要翻译：方法和设备使用交换性错误检测值（例如，校验和）识别和隔离故障节点，在多个节点计算系统中执行故障隔离。当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值。每隔一段时间，与多节点计算机系统相关联的节点故障检测装置检索与节点相关联的交换错误检测值并将其存储在存储器中。当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值并将其存储在存储器中。节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。值的差异表示可能的故障节点。

6. 发明申请

US20110272788A1 Computer system wafer integrating different dies in stacked master-slave structures 审中-公开
标题翻译：在堆叠的主从结构中集成不同模具的计算机系统晶片
公开(公告)号：US20110272788A1
公开(公告)日：2011-11-10
申请号：US12777177
申请日：2010-05-10
申请人： Kyu-hyoun Kim , Paul Coteus
发明人： Kyu-hyoun Kim , Paul Coteus
IPC分类号： H01L29/06 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
摘要： A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits.
摘要翻译：制造堆叠的3D集成电路结构，其具有用于管芯的公共图像设计，其允许切割的主管芯从公共晶片切割并切割成具有共同图像设计的晶片切割的切割从属裸片。在一个实施例中，在切割之前堆叠以形成晶片到晶片3D堆叠。主单元和从元件仅用于单个集成电路芯片切割分离之前沿着芯片边缘和模具中心位置的一种分离的单独集成电路管芯。主晶片沿模具移动1/2路，以便沿着切割线进行切割有效地提供主模和从模。多个从器件可以堆叠并耦合到主引脚，当连接到仅母模直接连接的总线时，主器件用作总线主器件。使用普通晶圆设计可最大限度地降低作为3D集成电路堆叠的芯片的制造成本。

7. 发明授权

US07897878B2 Compliant penetrating packaging interconnect 有权
标题翻译：兼容穿透包装互连
公开(公告)号：US07897878B2
公开(公告)日：2011-03-01
申请号：US11627430
申请日：2007-01-26
申请人： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
发明人： Paul Coteus , Gareth Geoffrey Hougham , Brian R. Sundlof
IPC分类号： H01R12/04 , H05K1/11 , H05K3/36
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49805 , H01L23/49811 , H01L2924/0002 , H05K3/28 , H05K3/325 , H05K3/4007 , H05K3/4015 , H05K2201/0367 , H05K2201/09745 , H05K2201/1059 , H05K2201/10719 , H05K2203/167 , Y02P70/613 , Y10T29/49126 , Y10T29/4913 , H01L2924/00
摘要： A circuit package is provided. The circuit package includes a plurality of electrically conductive pads located on a bottom surface of the circuit package, wherein at least one pad of the plurality of bottom surface pads has a recession for receiving an electrically conductive protrusion located on a substrate to which the circuit package is to be mounted.
摘要翻译：提供电路封装。电路封装包括位于电路封装的底表面上的多个导电焊盘，其中多个底表面焊盘中的至少一个焊盘具有用于接收位于基板上的导电突起的凹陷，电路封装将被安装。

8. 发明申请

US20080055851A1 METHOD AND APPARATUS FOR COOLING AN EQUIPMENT ENCLOSURE THROUGH CLOSED-LOOP LIQUID-ASSISTED AIR COOLING IN COMBINATION WITH DIRECT LIQUID COOLING 失效
公开(公告)号：US20080055851A1
公开(公告)日：2008-03-06
申请号：US11862289
申请日：2007-09-27
申请人： Shawn Hall , Shurong Tian , Paul Coteus , John Karidis , Evan Colgan , Robert Guernsey
发明人： Shawn Hall , Shurong Tian , Paul Coteus , John Karidis , Evan Colgan , Robert Guernsey
IPC分类号： H05K7/20
CPC分类号： H05K7/20754 , G06F1/20 , G06F2200/201
摘要： A method and an apparatus for cooling, preferably within an enclosure, a diversity of heat-generating components, with at least some of the components having high-power densities and others having low-power densities. Heat generated by the essentially relatively few high-power-density components, such as microprocessor chips for example, is removed by direct liquid cooling, whereas heat generated by the more numerous low-power or low-watt-density components, such as memory chips for example, is removed by liquid-assisted air cooling in the form of a closed loop comprising a plurality of heating and cooling zones that alternate along the air path.

9. 发明申请

US20080020601A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 失效
公开(公告)号：US20080020601A1
公开(公告)日：2008-01-24
申请号：US11865458
申请日：2007-10-01
申请人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
发明人： Gareth Hougham , Brian Beaman , Evan Colgan , Paul Coteus , Stefano Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

10. 发明申请

US20070286199A1 METHOD AND SYSTEM FOR PROVIDING IDENTIFICATION TAGS IN A MEMORY SYSTEM HAVING INDETERMINATE DATA RESPONSE TIMES 有权
标题翻译：在具有不确定性数据响应时间的记忆系统中提供识别标签的方法和系统
公开(公告)号：US20070286199A1
公开(公告)日：2007-12-13
申请号：US11843271
申请日：2007-08-22
申请人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
发明人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
IPC分类号： H04L12/56
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags. The memory controller also includes a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller. Input to the determining includes an upstream identification tag included in the received data packet. If the received data packet is determined to be in response to a request from the memory controller, then the received data packet is matched to the request, thereby allowing the memory controller to operate with indeterminate data response times.
摘要翻译：一种用于在具有不确定的数据响应时间的存储器系统中提供识别标签的方法和系统。示例性实施例包括存储器系统中的存储器控制器。存储器控制器包括用于经由上游信道接收数据分组的机制，所述数据分组包括上行识别标签。存储器控制器还包括具有用于有助于确定接收的数据分组是否响应于来自存储器控制器的请求的指令的机制。确定的输入包括包含在接收的数据分组中的上游标识标签。如果接收到的数据分组被确定为响应于来自存储器控制器的请求，则接收的数据分组与该请求匹配，从而允许存储器控制器以不确定的数据响应时间进行操作。

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