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    • 1. 发明申请
    • Methods and apparatus using commutative error detection values for fault isolation in multiple node computers
    • 使用多节点计算机故障隔离交换误差检测值的方法和装置
    • US20060248370A1
    • 2006-11-02
    • US11106069
    • 2005-04-14
    • Gheorghe AlmasiMatthias BlumrichDong ChenPaul CoteusAlan GaraMark GiampapaPhilip HeidelbergerDirk HoenickeSarabjeet SinghBurkhard Steinmacher-BurowTodd TakkenPavlos Vranas
    • Gheorghe AlmasiMatthias BlumrichDong ChenPaul CoteusAlan GaraMark GiampapaPhilip HeidelbergerDirk HoenickeSarabjeet SinghBurkhard Steinmacher-BurowTodd TakkenPavlos Vranas
    • G06F11/00
    • G06F11/1633
    • The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created; the node fault detection apparatus retrieves them and stores them in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in commutative error detection values indicate that the node may be faulty.
    • 本发明涉及在多节点计算系统中使用交换性错误检测值(例如校验和)识别和隔离故障节点来执行故障隔离的方法和装置。 在本发明中,形成多节点计算系统的节点被联网在一起,并且在程序执行期间通过网络传送信息彼此通信。 当与计算机程序的可再现部分相关联的信息被节点注入到网络中时,计算交换性错误检测值并将其存储在与节点相关联的交换错误检测装置中。 间歇地,与多节点计算机系统相关联的节点故障检测装置检索保存在与节点相关联的交换性错误检测装置中的交换性错误检测值,并将其存储在存储器中。 当多节点计算机系统再次执行计算机程序时,创建新的交换错误检测值; 节点故障检测装置检索它们并将其存储在存储器中。 节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。 交换性错误检测值的差异表明节点可能有故障。
    • 2. 发明申请
    • LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION
    • 低延迟存储器访问和同步
    • US20070204112A1
    • 2007-08-30
    • US11617276
    • 2006-12-28
    • Matthias BlumrichDong ChenPaul CoteusAlan GaraMark GiampapaPhilip HeidelbergerDirk HoenickeMartin OhmachtBurkhard Steinmacher-BurowTodd TakkenPavlos Vranas
    • Matthias BlumrichDong ChenPaul CoteusAlan GaraMark GiampapaPhilip HeidelbergerDirk HoenickeMartin OhmachtBurkhard Steinmacher-BurowTodd TakkenPavlos Vranas
    • G06F12/14
    • G06F12/0862G06F9/52G06F2212/6028
    • A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
    • 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源,并且每个共享资源在锁定设备内具有关联的锁,其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时,处理器仅具有访问资源的权限,并且处理器拥有锁的尝试仅需要单个加载操作,而不是传统的原子负载后跟存储,使得处理器 只执行读取操作,并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单预取。 重新定义存储器线,使得除了正常的物理存储器数据之外,每行包括足够大的指针以指向存储器中的任何其他行,其中指针用于确定要预取的存储器行而不是一些其它预测 算法。 这使得硬件能够有效地预取不连续但重复的存储器访问模式。