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1. 发明申请

US20060248370A1 Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
标题翻译：使用多节点计算机故障隔离交换误差检测值的方法和装置
公开(公告)号：US20060248370A1
公开(公告)日：2006-11-02
申请号：US11106069
申请日：2005-04-14
申请人： Gheorghe Almasi , Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Sarabjeet Singh , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Gheorghe Almasi , Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Sarabjeet Singh , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F11/00
CPC分类号： G06F11/1633
摘要： The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created; the node fault detection apparatus retrieves them and stores them in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in commutative error detection values indicate that the node may be faulty.
摘要翻译：本发明涉及在多节点计算系统中使用交换性错误检测值（例如校验和）识别和隔离故障节点来执行故障隔离的方法和装置。在本发明中，形成多节点计算系统的节点被联网在一起，并且在程序执行期间通过网络传送信息彼此通信。当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值并将其存储在与节点相关联的交换错误检测装置中。间歇地，与多节点计算机系统相关联的节点故障检测装置检索保存在与节点相关联的交换性错误检测装置中的交换性错误检测值，并将其存储在存储器中。当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值; 节点故障检测装置检索它们并将其存储在存储器中。节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。交换性错误检测值的差异表明节点可能有故障。

2. 发明申请

US20070204112A1 LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
标题翻译：低延迟存储器访问和同步
公开(公告)号：US20070204112A1
公开(公告)日：2007-08-30
申请号：US11617276
申请日：2006-12-28
申请人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Paul Coteus , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Burkhard Steinmacher-Burow , Todd Takken , Pavlos Vranas
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/52 , G06F2212/6028
摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.
摘要翻译：与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。还公开了用于非连续数据结构的简单预取。重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测算法。这使得硬件能够有效地预取不连续但重复的存储器访问模式。

3. 发明申请

US20050195808A1 Multidimensional switch network 失效
标题翻译：多维交换机网络
公开(公告)号：US20050195808A1
公开(公告)日：2005-09-08
申请号：US10793068
申请日：2004-03-04
申请人： Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas , Matthias Blumrich
发明人： Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas , Matthias Blumrich
IPC分类号： H04L12/26
CPC分类号： H04L49/1576 , H04L45/06
摘要： Multidimensional switch data networks are disclosed, such as are used by a distributed-memory parallel computer, as applied for example to computations in the field of life sciences. A distributed memory parallel computing system comprises a number of parallel compute nodes and a message passing data network connecting the compute nodes together. The data network connecting the compute nodes comprises a multidimensional switch data network of compute nodes having N dimensions, and a number/array of compute nodes Ln in each of the N dimensions. Each compute node includes an N port routing element having a port for each of the N dimensions. Each compute node of an array of Ln compute nodes in each of the N dimensions connects through a port of its routing element to an Ln port crossbar switch having Ln ports. Several embodiments are disclosed of a 4 dimensional computing system having 65,536 compute nodes.
摘要翻译：公开了多维交换机数据网络，例如由分布式存储器并行计算机使用的，例如应用于生命科学领域的计算。分布式存储器并行计算系统包括多个并行计算节点和将计算节点连接在一起的消息传递数据网络。连接计算节点的数据网络包括具有N维的计算节点的多维交换机数据网络和N个维度中的每一个中的计算节点Ln的数量/数组。每个计算节点包括具有用于N个维度中的每一个的端口的N端口路由元件。每个N维中的Ln计算节点阵列的每个计算节点通过其路由元素的端口连接到具有Ln端口的Ln端口交叉开关。公开了具有65,536个计算节点的四维计算系统的几个实施例。

4. 发明申请

US20060224837A1 Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture 有权
公开(公告)号：US20060224837A1
公开(公告)日：2006-10-05
申请号：US11093131
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/084 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

5. 发明申请

US20060224838A1 Novel snoop filter for filtering snoop requests 有权
标题翻译：用于过滤窥探请求的新型窥探过滤器
公开(公告)号：US20060224838A1
公开(公告)日：2006-10-05
申请号：US11093152
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与其可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求写入源并将这些请求的子集转发到其相关联的处理单元。

6. 发明申请

US20060224835A1 Snoop filtering system in a multiprocessor system 有权
标题翻译：多处理器系统中的Snoop过滤系统
公开(公告)号：US20060224835A1
公开(公告)日：2006-10-05
申请号：US11093127
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter unit corresponding to and in communication with a respective processing unit, with each snoop filter unit comprising a plurality of devices for receiving asynchronous snoop requests from respective memory writing sources in the computing environment; and a point-to-point interconnect comprising communication links for directly connecting memory writing sources to corresponding receiving devices; and, a plurality of parallel operating filter devices coupled in one-to-one correspondence with each receiving device for processing snoop requests received thereat and one of forwarding requests or preventing forwarding of requests to its associated processing unit. Each of the plurality of parallel operating filter devices comprises parallel operating sub-filter elements, each simultaneously receiving an identical snoop request and implementing one or more different snoop filter algorithms for determining those snoop requests for data that are determined not cached locally at the associated processing unit and preventing forwarding of those requests to the processor unit. In this manner, a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持高速缓存一致性的系统和方法，每个单元具有与其可操作耦合的相关联的高速缓存存储器系统该系统包括多个互连的窥探过滤器单元，每个窥探过滤器单元对应于相应处理单元并与其通信，每个窥探过滤器单元包括用于在计算环境中从相应存储器写入源接收异步窥探请求的多个设备 ; 以及包括用于将存储器写入源直接连接到对应的接收设备的通信链路的点对点互连; 以及与每个接收设备一一对应地耦合的多个并行操作过滤器设备，用于处理在其上接收的窥探请求，并且转发请求之一或者阻止将请求转发到其相关联的处理单元。多个并行操作过滤器装置中的每一个包括并行操作子滤波器元件，每个并行操作子滤波器元件同时接收相同的窥探请求，并且实现一个或多个不同的窥探滤波器算法，用于确定对于在相关处理中本地未被缓存的数据被确定的窥探请求并且防止将这些请求转发到处理器单元。以这种方式，减少了转发到处理单元的多个窥探请求，从而增加了计算环境的性能。

7. 发明申请

US20050002387A1 One-bounce network 失效
标题翻译：单反网络
公开(公告)号：US20050002387A1
公开(公告)日：2005-01-06
申请号：US10675129
申请日：2003-09-30
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： H04L12/56 , H04Q11/00
CPC分类号： H04L45/06
摘要： A one-bounce data network comprises a plurality of nodes interconnected to each other via communication links, the network including a plurality of interconnected switch devices, said switch devices interconnected such that a message is communicated between any two switches passes over a single link from a source switch to a destination switch; and, the source switch concurrently sends a message to an arbitrary bounce switch which then sends the message to the destination switch.
摘要翻译：一弹跳数据网络包括经由通信链路相互互连的多个节点，所述网络包括多个互连的交换设备，所述交换设备互连，使得在任何两个交换机之间传送的消息通过单个链路从源切换到目的地交换机; 并且，源交换机同时向任意的反弹交换机发送消息，然后将消息发送到目的地交换机。

8. 发明申请

US20070055825A1 Managing coherence via put/get windows 失效
标题翻译：通过put / get窗口管理一致性
公开(公告)号：US20070055825A1
公开(公告)日：2007-03-08
申请号：US10468995
申请日：2002-02-25
申请人： Matthias Blumrich , Dong Chan , Paul Coteus , Alan Gata , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias Blumrich , Dong Chan , Paul Coteus , Alan Gata , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F13/28
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

9. 发明申请

US20110173422A1 PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN 失效
标题翻译：暂停处理器硬件螺纹密码
公开(公告)号：US20110173422A1
公开(公告)日：2011-07-14
申请号：US12684860
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/44 , G06F15/00 , G06F9/06
CPC分类号： G06F9/30079 , G06F9/3851
摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
摘要翻译：一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。处理器处理来自程序的指令。处理器中的等待状态等待接收指定的数据。处理器中的线程具有暂停状态，其中处理器等待指定的数据。处理器中的引脚从线程的暂停状态启动返回到活动状态。逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。

10. 发明授权

US08447960B2 Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition 失效
标题翻译：通过外部逻辑监视轮询循环退出时间条件，在引脚断言时暂停和激活线程状态
公开(公告)号：US08447960B2
公开(公告)日：2013-05-21
申请号：US12684860
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/48
CPC分类号： G06F9/30079 , G06F9/3851
摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
摘要翻译：一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。处理器处理来自程序的指令。处理器中的等待状态等待接收指定的数据。处理器中的线程具有暂停状态，其中处理器等待指定的数据。处理器中的引脚从线程的暂停状态启动返回到活动状态。逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。

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