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1. 发明授权

US07217922B2 Planar micro-miniature ion trap devices 有权
标题翻译：平面微型离子阱装置
公开(公告)号：US07217922B2
公开(公告)日：2007-05-15
申请号：US11079861
申请日：2005-03-14
申请人： Matthew Douglas Apau Jachowski , Yee Leng Low , Stanley Pau
发明人： Matthew Douglas Apau Jachowski , Yee Leng Low , Stanley Pau
IPC分类号： B01D59/44 , H01J49/00
CPC分类号： H01J49/424 , H01J49/0018
摘要： A micro-miniature ion trap device comprises a wafer (or substrate) having a major surface, a multiplicity of electrodes forming a micro-miniature ion trap in a region adjacent the major surface when voltage is applied to the electrodes, characterized in that the multiplicity includes a first, planar annular electrode located over and rigidly affixed to the major surface, and at least one second, planar annular electrode located over and rigidly affixed to the major surface, the at least one second electrode being concentric with the first electrode. The at least one second electrode may be completely annular, in that the annulus forms a closed geometric shape, or it may be partially annular, in that the annulus has a slot or opening allowing access to the first electrode. In accordance with a preferred embodiment of our invention, the at least one second electrode is C-shaped, and the angle subtended by the C-shape is greater than 180 degrees.
摘要翻译：微型离子阱装置包括具有主表面的晶片（或衬底），当电压施加到电极时，在与主表面相邻的区域中形成微型离子阱的多个电极，其特征在于多重包括位于主表面上并刚性地固定到主表面上的第一平面环形电极和位于主表面上并刚性地固定到主表面上的至少一个第二平面环形电极，所述至少一个第二电极与第一电极同心。至少一个第二电极可以是完全环形的，因为环形部分形成封闭的几何形状，或者它可以是部分环形的，因为环形空间具有允许进入第一电极的槽或开口。根据本发明的优选实施例，所述至少一个第二电极是C形的，并且由C形形成的角度大于180度。

2. 发明授权

US06297551B1 Integrated circuit packages with improved EMI characteristics 有权
标题翻译：集成电路封装具有改进的EMI特性
公开(公告)号：US06297551B1
公开(公告)日：2001-10-02
申请号：US09401690
申请日：1999-09-22
申请人： Thomas Dixon Dudderar , Dean Paul Kossives , Yee Leng Low
发明人： Thomas Dixon Dudderar , Dean Paul Kossives , Yee Leng Low
IPC分类号： H01L2334
CPC分类号： H01L23/055 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L2224/05599 , H01L2224/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/3025 , H05K1/0218 , H05K1/141 , H05K3/3442 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099
摘要： The specification describes a recessed chip MCM package with integrated electromagnetic shielding. The surfaces of the cavity which houses the IC devices are coated with metallization. The normally exposed top and side surfaces of the MCM package are also metallized. A solder wall is provided on the interconnect PCB which seals the gap between the MCM tile and the PCB interconnect substrate. The solder wall can be formed using standard solder bump technology, and the seal between the MCM and the PCB may be made during the same reflow operation that is used to flip-chip bond the MCM tile to the PCB.
摘要翻译：该规范描述了具有集成电磁屏蔽的嵌入式芯片MCM封装。容纳IC器件的腔的表面涂有金属化。通常暴露的MCM封装的顶部和侧面也被金属化。在互连PCB上提供焊接壁，其密封MCM瓦片和PCB互连基板之间的间隙。可以使用标准焊料凸块技术形成焊接壁，并且可以在用于将MCM瓦片贴合到PCB的相同回流操作期间进行MCM和PCB之间的密封。

3. 发明授权

US06603182B1 Packaging micromechanical devices 失效
标题翻译：包装微机械装置
公开(公告)号：US06603182B1
公开(公告)日：2003-08-05
申请号：US10097072
申请日：2002-03-12
申请人： Yee Leng Low , David Andrew Ramsey
发明人： Yee Leng Low , David Andrew Ramsey
IPC分类号： H01L310232
CPC分类号： B81B7/0077 , H01L2224/48091 , H01L2224/48227 , H01L2924/09701 , H01L2924/10253 , H05K1/142 , H05K1/183 , H01L2924/00014 , H01L2924/00
摘要： The specification describes a packaging arrangement for micro-electromechanical systems (MEMS). The MEMS devices are mounted on a ceramic platform and are then packaged in a hybrid package. The hybrid package may be hermetically sealed. The hybrid package uses a ceramic insert as the primary MEMS device enclosure. The ceramic insert is mounted on a polymer printed wiring board, which provides both support and electrical interconnection for the ceramic insert. Optical access to the MEMS device is through a transparent window that may be hermetically sealed to the ceramic insert. The use of a ceramic primary enclosure for the MEMS device array substantially eliminates thermomechanical instabilities and provides thermomechanical and hermetic performance for the elements that require it. The main interconnection and routing function, implemented using standard epoxy printed circuit technology, yields high interconnection versatility and performance at low cost.
摘要翻译：本说明书描述了用于微机电系统（MEMS）的封装装置。 MEMS器件安装在陶瓷平台上，然后被封装在混合封装中。混合包装可以密封。混合封装使用陶瓷插件作为主要的MEMS器件外壳。陶瓷插入件安装在聚合物印刷线路板上，其为陶瓷插入件提供支撑和电互连。对MEMS器件的光学访问通过透明窗口，其可以与陶瓷插入件气密密封。使用用于MEMS器件阵列的陶瓷初级外壳基本上消除了热机械不稳定性并且为需要元件提供热机械和密封性能。使用标准环氧印刷电路技术实现的主要互连和布线功能以低成本产生高互连通用性和性能。

4. 发明授权

US6154370A Recessed flip-chip package 失效
标题翻译：嵌入式倒装芯片封装
公开(公告)号：US6154370A
公开(公告)日：2000-11-28
申请号：US120148
申请日：1998-07-21
申请人： Yinon Degani , Robert Charles Frye , Yee Leng Low
发明人： Yinon Degani , Robert Charles Frye , Yee Leng Low
IPC分类号： H01L23/12 , H01L23/498 , H01L23/50 , H05K1/18
CPC分类号： H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/17 , H05K1/182 , H01L2224/16145 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/1532
摘要： The specification describes a recessed chip IC package in which the cavity in the printed wiring board into which the IC chip is recessed is used as a through hole interconnection, thus increasing the interconnection density. If the through cavity interconnections are used as power and ground the signal I/O pads and the signal runners are effectively isolated.
摘要翻译：该说明书描述了一种嵌入式芯片IC封装，其中将IC芯片凹入的印刷电路板中的空腔用作通孔互连，从而增加了互连密度。如果使用通孔互连作为电源和接地，则信号I / O焊盘和信号通道有效隔离。

5. 发明授权

US06232047B1 Fabricating high-Q RF components 有权
标题翻译：制造高Q射频元件
公开(公告)号：US06232047B1
公开(公告)日：2001-05-15
申请号：US09261093
申请日：1999-03-02
申请人： Robert Charles Frye , Yee Leng Low , King Lien Tai
发明人： Robert Charles Frye , Yee Leng Low , King Lien Tai
IPC分类号： G03C500
CPC分类号： H05K3/246 , H01P11/003 , H05K1/0242 , H05K3/146 , H05K2201/0317
摘要： The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.
摘要翻译：该说明书描述了用于改善由厚膜糊技术形成的导电金属条的边缘敏锐度的方法。实现了使用厚膜技术形成的条的体积特性的优点，同时利用在导电条的边缘处的薄膜修剪带克服了差的边缘限定的缺点。

6. 发明授权

US5898223A Chip-on-chip IC packages 失效
标题翻译：片上芯片封装
公开(公告)号：US5898223A
公开(公告)日：1999-04-27
申请号：US946980
申请日：1997-10-08
申请人： Robert Charles Frye , Yee Leng Low , Kevin John O'Connor
发明人： Robert Charles Frye , Yee Leng Low , Kevin John O'Connor
IPC分类号： H01L25/18 , H01L23/522 , H01L23/538 , H01L25/065 , H01L25/07 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5221 , H01L23/5381 , H01L25/0652 , H01L2224/16145 , H01L25/18 , H01L2924/01322
摘要： The specification describes interconnection layouts for chip-on-chip packages using solder bump interchip connections as vias between a single level metal interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper IC chip. This arrangement allows for the formation of air isolated crossovers of features on either chip.
摘要翻译：该规范描述了使用焊料凸块芯片间连接作为芯片芯片封装的互连布局，作为下部支持IC芯片上的单级金属互连图案与上部IC芯片上的另一个单级互连图案之间的通孔。这种布置允许在任一芯片上形成特征的空气隔离交叉。

7. 发明授权

US06370766B1 Manufacture of printed circuit cards 失效
标题翻译：印刷电路卡的制造
公开(公告)号：US06370766B1
公开(公告)日：2002-04-16
申请号：US08807266
申请日：1997-02-28
申请人： Yinon Degani , Thomas Dixon Dudderar , Dean Paul Kossives , Yee Leng Low
发明人： Yinon Degani , Thomas Dixon Dudderar , Dean Paul Kossives , Yee Leng Low
IPC分类号： H05K330
CPC分类号： H05K1/0268 , G01R31/2818 , H05K3/0052 , Y10T29/4913 , Y10T29/49144
摘要： The specification describes methods for the manufacture of printed circuit cards which allow for final testing, including burn-in if required, of multiples of printed circuit cards as an integrated process panel prior to final packaging and singulation. This desired sequence of operations is made possible by the addition of arrays of test contacts at the edge of the integrated process panel where the test contacts can be accessed with an insertion test apparatus.
摘要翻译：本说明书描述了用于制造印刷电路卡的方法，其允许最终测试，包括如果需要，在最终包装和分割之前作为集成处理面板的多个印刷电路卡进行最终测试。通过在集成处理面板的边缘添加测试触点的阵列，可以使用插入测试装置访问测试触点，从而可以实现所需的操作顺序。

8. 发明授权

US06313719B1 Method of tuning a planar filter with additional coupling created by bent resonator elements 有权
标题翻译：通过由弯曲谐振器元件产生的附加耦合来调谐平面滤波器的方法
公开(公告)号：US06313719B1
公开(公告)日：2001-11-06
申请号：US09522450
申请日：2000-03-09
申请人： Ron Barnett , Yee Leng Low , Zhengxiang Ma , King L Tai , Hui Wu
发明人： Ron Barnett , Yee Leng Low , Zhengxiang Ma , King L Tai , Hui Wu
IPC分类号： H01P1203
CPC分类号： H01P1/20372
摘要： A bandpass planar filter (110) comprises a signal input and a signal output (116), and one or more resonator elements (112, 114) coupled serially end-to-end between the input and the output across gaps (118) that separate the elements from the input, the output, and from each other. The resonator elements form a serpentine shape such that at least two portions of the serpentine shape are positioned side-by-side parallel to each other separated by a spacing (120). The side-by-side portions effect additional coupling between the resonator elements that forms a notch (transmission zero) (204) in the passband (200) of the filter. The input, output, and resonator elements are etched into one surface (106) of a PC board (102); the other surface (104) of the PC board forms a ground plane of the filter, and the substrate (103) of the PC board forms a dielectric of the filter.
摘要翻译：带通平面滤波器（110）包括信号输入端和信号输出端（116），以及一个或多个谐振元件（112,114），它们跨接在间隔（118）上的输入端和输出端之间端对端地串联连接，来自输入，输出和彼此的元素。谐振器元件形成蛇形形状，使得蛇形形状的至少两部分彼此平行地彼此平行地间隔开间隔（120）。并排部分影响在滤波器的通带（200）中形成陷波（传输零点）（204）的谐振元件之间的附加耦合。输入，输出和谐振器元件被蚀刻到PC板（102）的一个表面（106）中; PC板的另一个表面（104）形成滤波器的接地平面，并且PC板的基板（103）形成滤波器的电介质。

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