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1. 发明授权

US08688961B2 Managing migration of a prefetch stream from one processor core to another processor core 失效
公开(公告)号：US08688961B2
公开(公告)日：2014-04-01
申请号：US13427045
申请日：2012-03-22
申请人： Matthew Accapadi , Robert H. Bell, Jr. , Hong Lam Hua , Ram Raghavan , Mysore Sathyanarayana Srinivas
发明人： Matthew Accapadi , Robert H. Bell, Jr. , Hong Lam Hua , Ram Raghavan , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

2. 发明授权

US08688960B2 Managing migration of a prefetch stream from one processor core to another processor core 有权
标题翻译：管理从一个处理器核心到另一个处理器核心的预取流的迁移
公开(公告)号：US08688960B2
公开(公告)日：2014-04-01
申请号：US12905176
申请日：2010-10-15
申请人： Matthew Accapadi , Robert H. Bell, Jr. , Hong Lam Hua , Ram Raghavan , Mysore Sathyanarayana Srinivas
发明人： Matthew Accapadi , Robert H. Bell, Jr. , Hong Lam Hua , Ram Raghavan , Mysore Sathyanarayana Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
摘要翻译：公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核的预取引擎可用性。如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

3. 发明授权

US08806153B2 Partial line cache write injector for direct memory access write 有权
标题翻译：部分行缓存写入注入器用于直接内存访问写入
公开(公告)号：US08806153B2
公开(公告)日：2014-08-12
申请号：US13031809
申请日：2011-02-22
申请人： Robert H. Bell, Jr. , Herman Dietrich Dierks , Hong Lam Hua , Mysore Sathyanarayana Srinivas
发明人： Robert H. Bell, Jr. , Herman Dietrich Dierks , Hong Lam Hua , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/04 , G06F11/10 , G06F12/12
CPC分类号： G06F12/04 , G06F11/1056 , G06F12/0806 , G06F12/0888 , G06F12/12 , G06F2212/621
摘要： A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.
摘要翻译：计算机系统内的高速缓存接收部分写请求并识别高速缓存行的高速缓存命中。高速缓存线对应于部分写入请求并且包括现有数据。反过来，高速缓存接收部分写入数据，并将部分写入数据与现有数据合并到高速缓存行中。在一个实施例中，现有数据被“修改”或“脏”。在另一个实施例中，现有数据是“共享”。在该实施例中，高速缓存改变高速缓存线的状态以指示部分写数据的存储进入缓存行。

4. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

5. 发明授权

US09323527B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
标题翻译：使用瞬态指令流在虚拟化环境中的新兴应用程序的性能
公开(公告)号：US09323527B2
公开(公告)日：2016-04-26
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以被写入L1和下级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

6. 发明授权

US09582284B2 Performance of processors is improved by limiting number of branch prediction levels 有权
标题翻译：通过限制分支预测级别的数量来提高处理器的性能
公开(公告)号：US09582284B2
公开(公告)日：2017-02-28
申请号：US13308696
申请日：2011-12-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
IPC分类号： G06F9/38 , G06F11/30
CPC分类号： G06F9/3844 , G06F9/3842 , G06F11/30 , G06F11/3024 , G06F11/3409 , G06F2201/81
摘要： A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.
摘要翻译：一种方法利用由性能监视硬件提供的信息来动态调整对于处理器核心允许的推测分支预测级别（通常为每线程3或4个）。该信息包括处理器核心的每个指令周期（CPI）和每单位时间的存储器访问次数。如果CPI低于CPI阈值; 并且每单位时间的存储器访问次数（NMA）高于规定的阈值，则对于处理器核，每个线程的推测分支预测的级别数量减少。同样地，如果超过CPI阈值或每单位时间的存储器访问次数低于规定的阈值，则可以将推测分支预测的级数从低级别增加到允许的最大级别。

7. 发明授权

US08943272B2 Variable cache line size management 有权
标题翻译：可变缓存行大小管理
公开(公告)号：US08943272B2
公开(公告)日：2015-01-27
申请号：US13451742
申请日：2012-04-20
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen , Diane G. Flemming , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0897
摘要： According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.
摘要翻译：根据本公开的一个方面，公开了一种用于可变高速缓存行大小管理的方法和技术。该方法包括：确定是否执行将高速缓存行从高级扇区高速缓存驱逐到未故障的较低级高速缓存，其中高级缓存包括多个子扇区，每个子扇区具有高速缓存行对应于较低级缓存的高速缓存行大小的大小; 响应于确定要执行驱逐，识别要被驱逐的高速缓存行的参考子扇区; 使要删除的缓存行的未引用子扇区无效; 并将所引用的子扇区存储在下级缓存中。

8. 发明授权

US08769210B2 Dynamic prioritization of cache access 有权
标题翻译：高速缓存访问的动态优先级
公开(公告)号：US08769210B2
公开(公告)日：2014-07-01
申请号：US13323076
申请日：2011-12-12
申请人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , William A. Maron , Mysore S. Srinivas
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an amount of cache resources used to service cache misses within a past period. In some embodiments, each of the cache state machines is configured to, determine whether a memory access request results in a cache miss or cache hit, and in response to a cache miss for a memory access request, query the tracking unit for the amount of cache resources used to service cache misses within the past period. In some embodiments, the each of the cache state machines is configured to service the memory access request based, at least in part, on the amount of cache resources used to service the cache misses within the past period according to the tracking unit.
摘要翻译：本发明主题的一些实施例涉及包括跟踪单元和高速缓存状态机的高速缓存。在一些实施例中，跟踪单元被配置为跟踪用于在过去时间段内服务高速缓存未命中的高速缓存资源的量。在一些实施例中，每个高速缓存状态机被配置为，确定存储器访问请求是否导致高速缓存未命中或高速缓存命中，并且响应于存储器访问请求的高速缓存未命中，查询跟踪单元的数量用于在过去一段时间内缓存未命中服务的缓存资源。在一些实施例中，每个高速缓存状态机被配置为至少部分地基于用于根据跟踪单元在过去时段内服务高速缓存未命中的高速缓存资源的量来服务存储器访问请求。

9. 发明授权

US08527956B2 Workload performance projection via surrogate program analysis for future information handling systems 失效
标题翻译：通过代理程序分析进行未来信息处理系统的工作负载性能预测
公开(公告)号：US08527956B2
公开(公告)日：2013-09-03
申请号：US12343467
申请日：2008-12-23
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F9/44
CPC分类号： G06F11/3419 , G06F11/3414 , G06F11/3457 , G06F2201/865 , G06F2201/88
摘要： A performance projection system includes a test IHS and multiple currently existing IHSs. The performance projection system includes user application software and surrogate programs that execute on currently existing IHSs. The performance projection system measures user application software and surrogate program performance during execution on currently existing IHSs. The performance projection systems measures runtime program performance during execution of surrogate programs on a future semiconductor die IC design model or virtualized future system. Designers normalize and compare surrogate program runtime performance data with user application software performance data. Designers un-normalize the normalized runtime performance data to generate a projection of runtime performance on the future system.
摘要翻译：性能投影系统包括测试IHS和多个当前存在的IHS。性能投影系统包括在当前存在的IHS上执行的用户应用软件和代理程序。性能投影系统在目前现有的IHSs的执行过程中测量用户应用软件和代理程序性能。性能投影系统在未来的半导体芯片IC设计模型或虚拟化未来系统执行替代程序期间测量运行时程序性能。设计师将代理程序运行时性能数据与用户应用软件性能数据进行规范化和比较。设计师对规范化的运行时性能数据进行非规范化，以生成对未来系统的运行时性能的投影。

10. 发明授权

US07996346B2 Method for autonomic workload distribution on a multicore processor 有权
标题翻译：多核处理器上自主工作量分配的方法
公开(公告)号：US07996346B2
公开(公告)日：2011-08-09
申请号：US11959520
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
IPC分类号： G06F15/18 , G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5083
摘要： A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.
摘要翻译：一个包含自动工作负载分配的多处理器系统。当线程在多处理器系统中执行时，操作系统或管理程序将持续学习线程的执行特性，并将信息保存在线程特定的控制块中。执行特性用于生成线程性能数据。当线程执行时，操作系统会持续使用性能数据来将线程引导到最高效执行工作负载的内核。

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