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1. 发明授权

US4933576A Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit 失效
标题翻译：具有用于形成主从触发器电路的主单元和从单元的宏单元的门阵列器件
公开(公告)号：US4933576A
公开(公告)日：1990-06-12
申请号：US349076
申请日：1989-05-09
申请人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
发明人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
IPC分类号： H03K3/037 , H03K19/086 , H03K19/173
CPC分类号： H03K19/1735 , H03K19/0866 , H03K3/0372 , Y10S257/923
摘要： A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.

2. 发明授权

US4928024A Referenceless ECL logic circuit 失效
标题翻译：无参考ECL逻辑电路
公开(公告)号：US4928024A
公开(公告)日：1990-05-22
申请号：US344405
申请日：1989-04-28
申请人： Isao Shimotsuhama , Shinji Emori , Yoshio Watanabe , Masaya Tamamura
发明人： Isao Shimotsuhama , Shinji Emori , Yoshio Watanabe , Masaya Tamamura
IPC分类号： H03K19/086 , H03K19/094
CPC分类号： H03K19/086 , H03K19/09436
摘要： An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

3. 发明授权

US5001361A Master-slave flip-flop circuit 失效
标题翻译：主从触发器电路
公开(公告)号：US5001361A
公开(公告)日：1991-03-19
申请号：US349251
申请日：1989-05-09
申请人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
发明人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
IPC分类号： H03K3/289
CPC分类号： H03K3/289
摘要： A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals responsive to the clock signal and outputs at least one of the held complementary output signals. The complementary output signals of the master part have a logic amplitude which is smaller than a logic amplitude of the output signal of the slave part to ensure correct operation even when the data signal and the clock signal have high frequencies.

4. 发明授权

US5270586A Controllable delay logic circuit for providing variable delay time 失效
标题翻译：用于提供可变延迟时间的可控延迟逻辑电路
公开(公告)号：US5270586A
公开(公告)日：1993-12-14
申请号：US766531
申请日：1990-10-31
申请人： Shinji Emori , Masaya Tamamura
发明人： Shinji Emori , Masaya Tamamura
IPC分类号： H03K5/13 , H03K19/086 , H03K19/20
CPC分类号： H03K5/13
摘要： A controllable delay logic circuit includes a differential circuit having first and second transistors, a first load coupled between a first power supply line and the collector of the first transistor, a second load coupled between the first power supply line and the collector of the second transistor, and a constant-current source connected between a second power supply line and the emitters of the first and second transistors. The controllable delay logic circuit also includes a first power source, a first current path circuit having a first resistor and selectively allowing a first current to pass through the first transistor from the first power source via the first resistor, and a second current path circuit having a second resistor and selectively allowing a second current to pass through the second transistor from the first power source via the second resistor.
摘要翻译：可控延迟逻辑电路包括具有第一和第二晶体管的差分电路，耦合在第一电源线和第一晶体管的集电极之间的第一负载，耦合在第一电源线和第二晶体管的集电极之间的第二负载以及连接在第二电源线和第一和第二晶体管的发射极之间的恒流源。可控延迟逻辑电路还包括第一电源，第一电流路径电路，具有第一电阻器，并且选择性地允许第一电流经由第一电阻器从第一电源通过第一晶体管;以及第二电流通路电路，其具有第二电阻器，并且选择性地允许第二电流经由第二电阻器从第一电源通过第二晶体管。

5. 发明授权

US5128673A Signal generator for generating a delayed clock signal 失效
标题翻译：用于产生延迟时钟信号的信号发生器
公开(公告)号：US5128673A
公开(公告)日：1992-07-07
申请号：US540636
申请日：1990-06-20
申请人： Masaya Tamamura , Shinji Emori
发明人： Masaya Tamamura , Shinji Emori
IPC分类号： H03M9/00 , H04J3/04 , H04J3/06
CPC分类号： H04J3/047 , H04J3/0685
摘要： A signal generator having a Johnson counter including a plurality of flip-flops having CLOCK inputs to which a clock signal is inputted; a logic gate to which the clock signal and Q outputs of the flip-flops are inputted, the logic gate being constructed such that the clock signal is passed therethrough each time 2n clock pulses of the clock signal occur and that the logic gate outputs its output as a first signal, n representing the number of the flip-flops of the Johnson counter; and delay means for delaying the clock signal by a time corresponding to an input-output delayed time of the logic gate and for outputting the delayed clock signal as a second signal.

6. 发明授权

US4587444A Variable-threshold-type differential signal receiver 失效
标题翻译：可变阈值型差分信号接收机
公开(公告)号：US4587444A
公开(公告)日：1986-05-06
申请号：US513057
申请日：1983-07-12
申请人： Shinji Emori , Yoshio Watanabe
发明人： Shinji Emori , Yoshio Watanabe
IPC分类号： H04L25/03 , H03K3/2897 , H03K5/08 , H03K5/24 , H03K19/003 , H03K19/086
CPC分类号： H03K5/2418 , H03K3/2897
摘要： A variable-threshold-type differential signal receiver comprises a differential amplifier for comparing differential voltages of differential input signals with a predetermined threshold voltage so as to provide logical output signals. It further comprises an emitter follower and an impedance means, the output of the emitter follower being superimposed through the impedance means on one of the differential input signals, whereby the predetermined threshold voltage is variably controlled by controlling the input voltage of the first emitter follower.
摘要翻译：可变阈值型差分信号接收机包括差分放大器，用于将差分输入信号的差分电压与预定阈值电压进行比较，以便提供逻辑输出信号。它还包括射极跟随器和阻抗装置，射极跟随器的输出通过阻抗装置叠加在差分输入信号之一上，由此通过控制第一射极跟随器的输入电压来可变地控制预定阈值电压。

7. 发明授权

US4920406A Semiconductor device 失效
公开(公告)号：US4920406A
公开(公告)日：1990-04-24
申请号：US124944
申请日：1987-10-07
申请人： Yoshio Watanabe , Shinji Emori
发明人： Yoshio Watanabe , Shinji Emori
IPC分类号： H01L23/538 , H01L23/64 , H05K1/02 , H05K1/18 , H05K3/34
CPC分类号： H01L24/06 , H01L23/538 , H01L23/64 , H01L24/49 , H05K1/0243 , H01L2224/0401 , H01L2224/05553 , H01L2224/05644 , H01L2224/16225 , H01L2224/32188 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/3011 , H01L2924/30111 , H05K1/182 , H05K1/184 , H05K2201/10689 , H05K2201/10969 , H05K3/3421
摘要： A semiconductor device provided with a pair of package leads with external ends respectively and electrically connected to a drive side transmission line and a terminating side transmission line, as package leads of an integrated circuit to which signals transmitted from a drive circuit are input, the internal ends of the pair of package leads being electrically connected through pads on the chip. The pads on the chip may be connected to the package lead connected to the drive side transmission line and the terminating resistor.

8. 发明授权

US4827327A Integrated circuit device having stacked conductive layers connecting circuit elements therethrough 失效
标题翻译：集成电路器件，其具有通过其连接电路元件的堆叠导电层
公开(公告)号：US4827327A
公开(公告)日：1989-05-02
申请号：US214838
申请日：1988-07-05
申请人： Akira Miyauchi , Hiroshi Nishimoto , Tadashi Okiyama , Hiroo Kitasagami , Masahiro Sugimoto , Haruo Tamada , Shinji Emori
发明人： Akira Miyauchi , Hiroshi Nishimoto , Tadashi Okiyama , Hiroo Kitasagami , Masahiro Sugimoto , Haruo Tamada , Shinji Emori
IPC分类号： H01L23/12 , H01L21/60 , H01L23/057 , H01L23/498 , H01L23/64 , H01P1/00 , H01P3/08 , H01P5/00 , H01P5/02 , H01P5/08 , H05K1/02 , H05K1/18 , H05K3/32 , H05K3/40 , H01L23/14 , H01L23/52
CPC分类号： H05K1/184 , H01L23/057 , H01L23/49822 , H01L23/645 , H01L24/49 , H05K1/0243 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4903 , H01L2224/49051 , H01L2224/49175 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01057 , H01L2924/01061 , H01L2924/01072 , H01L2924/01074 , H01L2924/01082 , H01L2924/10329 , H01L2924/12041 , H01L2924/1306 , H01L2924/14 , H01L2924/16195 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H05K2201/10265 , H05K2201/10409 , H05K2201/10689 , H05K3/325 , H05K3/4046
摘要： An integrated circuit device including a stacked layer unit having a plurality of stacked layers each having an insulation layer and at least one conductive layer strip formed on a surface of the insulation layer, and at least one chip mounted on the top of the insulation layer and having a plurality of circuit elements. The IC device also includes at least one first conductive member formed in the stacked layer unit, having a low inductance for first signals applied thereto and operatively connecting the first signals to be transferred between the circuit elements. The IC device further includes at least one second conductive member formed in the stacked layer unit, having a higher inductance for the first signals than that of the first conductive member and operatively connecting second signals to be transferred between the circuit elements the stacked layer unit, the chip, and the first and second conductive members are enclosed by a package and sealed with a hermetic seal.
摘要翻译：一种集成电路器件，包括具有多个堆叠层的堆叠层单元，每个堆叠层具有绝缘层和形成在所述绝缘层的表面上的至少一个导电层条，以及安装在所述绝缘层的顶部上的至少一个芯片，具有多个电路元件。该IC器件还包括形成在堆叠层单元中的至少一个第一导电构件，对施加到其上的第一信号具有低电感，并可操作地连接要在电路元件之间传输的第一信号。 IC器件还包括形成在层叠单元中的至少一个第二导电构件，其具有比第一导电构件的第一信号更高的电感，并可操作地连接要在层叠单元的电路元件之间传输的第二信号，芯片和第一和第二导电构件被封装封装并用气密密封密封。

9. 发明授权

US4748346A Driver for differential signal transmission 失效
标题翻译：驱动器用于差分信号传输
公开(公告)号：US4748346A
公开(公告)日：1988-05-31
申请号：US683495
申请日：1984-12-19
申请人： Shinji Emori
发明人： Shinji Emori
IPC分类号： H04L25/02 , H03K5/02 , H03K3/01 , G06G7/12 , H03K17/16 , H03K19/086
CPC分类号： H03K5/02
摘要： A driver for transmitting a digital differential signal along a transmission line during a packet time and not during an idle time while maintaining a constant common voltage between the transmission line and ground throughout the packet and idle time periods. A driving circuit and its drive controller in the driver and respectively formed from paired matched transistors which function as on-off switching circuits and have a common emitter load acting as a constant current source. A collector of a first transistor in the drive controller is connected to the common emitter of the driving circuit and a collector of a second transistor in the drive controller is respectively connected to the collectors of the pair of transistors of the driving circuit through respective matched diodes. During the idle time, the driving circuit is cut off by the first transistor being cut off, and the second transistor carries collector current, which is separated into halves, through respective matched collector resistors in the driving circuit and the matched diodes. The voltage on each collector in the pair of transistors in the driving circuit becomes the mean value of a high and a low voltage levels produced during the packet time. The constant common voltage can be obtained from this mean voltage by using emitter followers. Matched transistors can be used instead of the matched diodes.
摘要翻译：一种用于在分组时间期间而不是在空闲时间期间沿着传输线发送数字差分信号的驱动器，同时在整个分组和空闲时间段期间保持传输线和地之间的恒定公共电压。驱动电路及其驱动控制器，分别由成对匹配的晶体管形成，该晶体管用作开 - 关开关电路，并具有作为恒流源的共同发射极负载。驱动控制器中的第一晶体管的集电极连接到驱动电路的公共发射极，并且驱动控制器中的第二晶体管的集电极分别通过相应的匹配二极管连接到驱动电路的该对晶体管的集电极。在空闲时间期间，驱动电路被截止的第一晶体管截止，并且第二晶体管通过驱动电路和匹配二极管中的相应匹配的集电极电阻将集电极电流分成两半。驱动电路中的一对晶体管中的每个集电极上的电压成为在分组时间期间产生的高电平和低电压电平的平均值。通过使用发射极跟随器可以从该平均电压获得恒定的公共电压。可以使用匹配的晶体管来代替匹配的二极管。

10. 发明授权

US4748350A Emitter-coupled logic circuit 失效
标题翻译：发射极耦合逻辑电路
公开(公告)号：US4748350A
公开(公告)日：1988-05-31
申请号：US105443
申请日：1987-10-02
申请人： Shinji Emori
发明人： Shinji Emori
IPC分类号： H03K19/00 , H03K19/003 , H03K19/086 , H03K19/20
CPC分类号： H03K19/00307 , H03K19/086
摘要： An emitter-coupled logic (ECL) circuit having a pull-down resistor and including a breakdown protecting structure. Such breakdown occurs in an input transistor for receiving input data when an excess reverse voltage is applied across the emitter and base of the input transistor. The breakdown protection structure preferably includes a constant-voltage regulating device which can always clamp the level of a reference voltage V.sub.BB to a suitable level higher than a low voltage V.sub.EE of a power source by the value of a constant voltage. The reference voltage V.sub.BB is usually applied to the base of another transistor which should be coupled, at respective emitters, with the input transistor by the representative emitters.
摘要翻译：具有下拉电阻并且包括击穿保护结构的发射极耦合逻辑（ECL）电路。当在输入晶体管的发射极和基极两端施加过量的反向电压时，这种击穿发生在用于接收输入数据的输入晶体管中。击穿保护结构优选地包括恒定电压调节装置，其可以总是将参考电压VBB的电平钳制到比电源的低电压VEE高的恒定电压值的适当电平。参考电压VBB通常被施加到另一个晶体管的基极，该晶体管应该在各个发射极处由代表性的发射极与输入晶体管耦合。

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