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1. 发明授权

US4928024A Referenceless ECL logic circuit 失效
标题翻译：无参考ECL逻辑电路
公开(公告)号：US4928024A
公开(公告)日：1990-05-22
申请号：US344405
申请日：1989-04-28
申请人： Isao Shimotsuhama , Shinji Emori , Yoshio Watanabe , Masaya Tamamura
发明人： Isao Shimotsuhama , Shinji Emori , Yoshio Watanabe , Masaya Tamamura
IPC分类号： H03K19/086 , H03K19/094
CPC分类号： H03K19/086 , H03K19/09436
摘要： An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

2. 发明授权

US4933576A Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit 失效
标题翻译：具有用于形成主从触发器电路的主单元和从单元的宏单元的门阵列器件
公开(公告)号：US4933576A
公开(公告)日：1990-06-12
申请号：US349076
申请日：1989-05-09
申请人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
发明人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
IPC分类号： H03K3/037 , H03K19/086 , H03K19/173
CPC分类号： H03K19/1735 , H03K19/0866 , H03K3/0372 , Y10S257/923
摘要： A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.

3. 发明授权

US5001361A Master-slave flip-flop circuit 失效
标题翻译：主从触发器电路
公开(公告)号：US5001361A
公开(公告)日：1991-03-19
申请号：US349251
申请日：1989-05-09
申请人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
发明人： Masaya Tamamura , Shinji Emori , Yoshio Watanabe , Isao Shimotsuhama
IPC分类号： H03K3/289
CPC分类号： H03K3/289
摘要： A master-slave flip-flop circuit is made up of a master part which holds a data signal responsive to a clock signal and outputs the held data signal in the form of complementary output signals, and a slave part which holds the complementary output signals responsive to the clock signal and outputs at least one of the held complementary output signals. The complementary output signals of the master part have a logic amplitude which is smaller than a logic amplitude of the output signal of the slave part to ensure correct operation even when the data signal and the clock signal have high frequencies.

4. 发明授权

US5128673A Signal generator for generating a delayed clock signal 失效
标题翻译：用于产生延迟时钟信号的信号发生器
公开(公告)号：US5128673A
公开(公告)日：1992-07-07
申请号：US540636
申请日：1990-06-20
申请人： Masaya Tamamura , Shinji Emori
发明人： Masaya Tamamura , Shinji Emori
IPC分类号： H03M9/00 , H04J3/04 , H04J3/06
CPC分类号： H04J3/047 , H04J3/0685
摘要： A signal generator having a Johnson counter including a plurality of flip-flops having CLOCK inputs to which a clock signal is inputted; a logic gate to which the clock signal and Q outputs of the flip-flops are inputted, the logic gate being constructed such that the clock signal is passed therethrough each time 2n clock pulses of the clock signal occur and that the logic gate outputs its output as a first signal, n representing the number of the flip-flops of the Johnson counter; and delay means for delaying the clock signal by a time corresponding to an input-output delayed time of the logic gate and for outputting the delayed clock signal as a second signal.

5. 发明授权

US5270586A Controllable delay logic circuit for providing variable delay time 失效
标题翻译：用于提供可变延迟时间的可控延迟逻辑电路
公开(公告)号：US5270586A
公开(公告)日：1993-12-14
申请号：US766531
申请日：1990-10-31
申请人： Shinji Emori , Masaya Tamamura
发明人： Shinji Emori , Masaya Tamamura
IPC分类号： H03K5/13 , H03K19/086 , H03K19/20
CPC分类号： H03K5/13
摘要： A controllable delay logic circuit includes a differential circuit having first and second transistors, a first load coupled between a first power supply line and the collector of the first transistor, a second load coupled between the first power supply line and the collector of the second transistor, and a constant-current source connected between a second power supply line and the emitters of the first and second transistors. The controllable delay logic circuit also includes a first power source, a first current path circuit having a first resistor and selectively allowing a first current to pass through the first transistor from the first power source via the first resistor, and a second current path circuit having a second resistor and selectively allowing a second current to pass through the second transistor from the first power source via the second resistor.
摘要翻译：可控延迟逻辑电路包括具有第一和第二晶体管的差分电路，耦合在第一电源线和第一晶体管的集电极之间的第一负载，耦合在第一电源线和第二晶体管的集电极之间的第二负载以及连接在第二电源线和第一和第二晶体管的发射极之间的恒流源。可控延迟逻辑电路还包括第一电源，第一电流路径电路，具有第一电阻器，并且选择性地允许第一电流经由第一电阻器从第一电源通过第一晶体管;以及第二电流通路电路，其具有第二电阻器，并且选择性地允许第二电流经由第二电阻器从第一电源通过第二晶体管。

6. 发明授权

US06535566B1 Demodulating method and receiver apparatus 有权
标题翻译：解调方法和接收装置
公开(公告)号：US06535566B1
公开(公告)日：2003-03-18
申请号：US09298052
申请日：1999-04-22
申请人： Masaya Tamamura , Ken Yamauchi
发明人： Masaya Tamamura , Ken Yamauchi
IPC分类号： H04L2500
CPC分类号： H04L27/38 , H04L27/22
摘要： A demodulating method demodulates a received signal received by a demodulator unit by detecting an absolute phase of signal points of the received signal. The demodulating method includes a first step of detecting the absolute phase by a first phase detecting method, a second step of detecting the absolute phase by a second phase detecting method in parallel with the first step, where the second phase detecting method has a slower detection speed or a higher detection accuracy than the first phase detecting method, and a third step of determining the absolute phase based on a phase detection result of the first step when phase detection results of the first and second steps are the same, and determining the absolute phase based on the phase detection result of the second step when the phase detection results of the first and second steps are different.
摘要翻译：解调方式通过检测接收信号的信号点的绝对相位来解调由解调器单元接收的接收信号。解调方法包括：通过第一相位检测方法检测绝对相位的第一步骤，与第一步骤并行地通过第二相位检测方法检测绝对相位的第二步骤，其中第二相位检测方法具有较慢的检测速度或更高的检测精度;以及第三步骤，当第一和第二步骤的相位检测结果相同时，基于第一步骤的相位检测结果确定绝对相位，并且确定绝对值当第一和第二步骤的相位检测结果不同时，基于第二步骤的相位检测结果的相位。

7. 发明授权

US5218230A IC package with electric conductor lines in dielectric package body 失效
标题翻译： IC封装与导电线路在电介质包装体
公开(公告)号：US5218230A
公开(公告)日：1993-06-08
申请号：US751094
申请日：1991-08-28
申请人： Masaya Tamamura , Yoshiro Morino
发明人： Masaya Tamamura , Yoshiro Morino
IPC分类号： H01L23/12 , H01L23/057 , H01L23/498 , H01L23/64 , H01P1/00 , H01P3/08
CPC分类号： H01L23/057 , H01L23/49822 , H01L23/64 , H01L24/49 , H01L2224/16 , H01L2224/32188 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/49171 , H01L2224/73253 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/16195 , H01L2924/3011 , H01L2924/30111
摘要： An IC package comprising a dielectric package body for encapsulating the semiconductor chip (31) and including a bottom member (1), first and second dielectric annular members (3, 7) surrounding the semiconductor chip, and a cap member (10). A first portion of the upper surface of the first dielectric annular member (3) is covered by the second dielectric annular member and a second portion of the upper surface of the first dielectric annular member (3) is exposed, whereby a strip line (Za) is formed by the second conductor film (8), the electric conductor lines (5 and 6), and a first covered portion of the first conductor film (4), and a microstrip line (Zb) is formed by the electric conductor lines (5 and 6), and a second exposed portion of the first conductor film (4). A third conductor film (9a and 9b) to be grounded is provided in the first dielectric annular member (3) in correspondence with second exposed portion of the first dielectric annular member ( 3), which is closer to the conductor lines (5 and 6) than the first conductor film (4) and constituting, with the conductor lines, a further microstrip line (Zb).
摘要翻译：一种IC封装，包括用于封装半导体芯片（31）并包括底部构件（1）的电介质封装主体，围绕半导体芯片的第一和第二介电环形构件（3,7）和盖构件（10）。第一介电环形构件（3）的上表面的第一部分被第二介电环形构件覆盖，并且第一介电环形构件（3）的上表面的第二部分被暴露，由此将带状线（Za ）由第二导体膜（8），导电线（5和6）以及第一导体膜（4）的第一覆盖部分形成，并且微带线（Zb）由导电线（5和6）和第一导体膜（4）的第二暴露部分。与第一电介质环形构件（3）的第二暴露部分相对应地设置在第一电介质环形构件（3）中的要接地的第三导体膜（9a和9b），其更靠近导体线（5和 6）。第三导体膜（9a，9b）将微带线（Zb）的阻抗与带状线（Za）的阻抗匹配。还可以包括另外的导体（9c，14）以减小电源导线（5）的阻抗。

8. 发明授权

US06087869A Digital PLL circuit 有权
标题翻译：数字PLL电路
公开(公告)号：US06087869A
公开(公告)日：2000-07-11
申请号：US166592
申请日：1998-10-06
申请人： Syouji Ohishi , Masaya Tamamura , Koichi Hatta
发明人： Syouji Ohishi , Masaya Tamamura , Koichi Hatta
IPC分类号： H03L7/06 , H03L7/08 , H03L7/085 , H03L7/091 , H03L7/095 , H03L7/10 , H04L7/033
CPC分类号： H04L7/0334 , H03L7/085 , H03L7/091 , H03L7/095 , H03L7/10 , H03L2207/50
摘要： A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.
摘要翻译：数字PLL电路从模拟基带信号中恢复时钟信号。 PLL电路具有相位比较器。在进行确定之后，相位比较器提供具有控制值的环路滤波器，用于恢复的时钟信号的周期。如果确定基带信号已经超过转换电平，则控制值对应于基带信号的采样点和转换电平交叉点之间的时间差。如果确定基带信号没有越过转换电平，则控制值为0. PLL电路缩短锁定时间，即使基带信号涉及偏移量也能提供稳定的操作。

9. 发明授权

US6078633A PLL circuit and its automatic adjusting circuit 失效
标题翻译： PLL电路及其自动调节电路
公开(公告)号：US6078633A
公开(公告)日：2000-06-20
申请号：US923640
申请日：1997-09-04
申请人： Shinichi Shiotsu , Masaya Tamamura
发明人： Shinichi Shiotsu , Masaya Tamamura
IPC分类号： H03L7/095 , H03L7/099 , H03L7/10 , H03L7/183 , H03D3/24
CPC分类号： H03L7/183 , H03L7/0991 , H03L7/10 , H03L2207/06 , H03L7/095
摘要： A 1/N programmable frequency divider for dividing the frequency of an output clock CLK1 from a VCO is connected between the VCO and a phase comparator in a PLL circuit. An adjusting circuit includes a counter for detecting a half-value of the frequency and for addressing a table ROM to make it read out a program data N and target value TV, a counter for detecting a half-value of the frequency of the output clock CLK from the 1/N programmable frequency divider, a digital comparator for comparing the count value of the counter and the target value TV and an up/down counter for incrementing or decrementing is count CFV in accordance with the comparison result, the count CFV being provided to the control input of the VCO.
摘要翻译：用于将来自VCO的输出时钟CLK1的频率分频的1 / N可编程分频器连接在VCO和PLL电路中的相位比较器之间。调整电路包括用于检测频率的半值的计数器，以及寻址表ROM以使其读出节目数据N和目标值TV的计数器，用于检测输出时钟频率的半值的计数器来自1 / N可编程分频器的CLK，用于比较计数器的计数值和目标值TV的数字比较器和用于递增或递减的加/减计数器是根据比较结果计数CFV，计数CFV为提供给VCO的控制输入。

10. 发明授权

US6118316A Semiconductor integrated circuit including plurality of phase-locked loops 失效
标题翻译：半导体集成电路包括多个锁相环
公开(公告)号：US6118316A
公开(公告)日：2000-09-12
申请号：US749672
申请日：1996-11-15
申请人： Masaya Tamamura , Syouji Ohishi
发明人： Masaya Tamamura , Syouji Ohishi
IPC分类号： H03K3/282 , H03K3/03 , H03L7/08 , H03L7/093 , H03L7/099 , H03L7/22 , H03L7/23 , H04L7/033 , H03L7/085
CPC分类号： H03L7/23 , H03L7/099 , H03L7/0995 , H03L7/0997 , H04L7/033
摘要： A semiconductor integrated circuit generating a stabilized oscillation signal based on an input signal includes a plurality of unit circuits connected in series, each of the unit circuits having at least an oscillator, a divider, and a phase comparator which construct at least one part of a phase-locked loop. In the unit circuit, a frequency of an oscillation output signal of a latter one of the unit circuits is higher than that of an oscillation output signal of a former one of the unit circuits.
摘要翻译：基于输入信号产生稳定振荡信号的半导体集成电路包括串联连接的多个单元电路，每个单元电路至少具有振荡器，分频器和相位比较器，其构成至少一部分锁相环。在单位电路中，后一个单位电路的振荡输出信号的频率高于前一个单位电路的振荡输出信号的频率。

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