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1. 发明授权

US09762246B2 Semiconductor device with a storage circuit having an oxide semiconductor 有权
公开(公告)号：US09762246B2
公开(公告)日：2017-09-12
申请号：US13469143
申请日：2012-05-11
申请人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
发明人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17772 , H03K19/17776
摘要： An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

2. 发明申请

US20120293201A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120293201A1
公开(公告)日：2012-11-22
申请号：US13469143
申请日：2012-05-11
申请人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
发明人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17772 , H03K19/17776
摘要： An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.
摘要翻译：目的是提供即使在电源电压停止之后也能够维持逻辑电路单元之间的连接关系或每个逻辑电路单元的电路配置的半导体器件。另一个目的是提供一种半导体器件，其中可以高速地改变逻辑电路单元之间的连接关系或每个逻辑电路单元的电路配置。在可重构电路中，氧化物半导体用于存储关于电路配置，连接关系等的数据的半导体元件。具体地，氧化物半导体用于半导体元件的沟道形成区域。

3. 发明申请

US20120195115A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120195115A1
公开(公告)日：2012-08-02
申请号：US13356828
申请日：2012-01-24
申请人： Masashi Fujita , Yutaka Shionoiri , Hiroyuki Tomatsu , Hidetomo Kobayashi
发明人： Masashi Fujita , Yutaka Shionoiri , Hiroyuki Tomatsu , Hidetomo Kobayashi
IPC分类号： G11C11/34 , H01L27/108
CPC分类号： H01L27/1225 , H01L21/84 , H01L27/088 , H01L27/108 , H01L27/1156 , H01L27/1203 , H01L27/1222 , H01L27/1251
摘要： A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.
摘要翻译：提供在绝缘区域上方设置有在第一半导体区域和第二半导体区域上设置绝缘区域的衬底上的第一场效应晶体管; 设置在所述基板上的绝缘层; 第二场效应晶体管，其设置在所述绝缘层的一个平面上，并且包括氧化物半导体层; 并提供控制终端。控制端子以与第二场效应晶体管的源极和漏极相同的步骤形成，并且用于控制第一场效应晶体管的阈值电压的电压被提供给控制端子。

4. 发明授权

US08937304B2 Semiconductor device and electronic device 有权
标题翻译：半导体器件和电子器件
公开(公告)号：US08937304B2
公开(公告)日：2015-01-20
申请号：US13356828
申请日：2012-01-24
申请人： Masashi Fujita , Yutaka Shionoiri , Hiroyuki Tomatsu , Hidetomo Kobayashi
发明人： Masashi Fujita , Yutaka Shionoiri , Hiroyuki Tomatsu , Hidetomo Kobayashi
IPC分类号： H01L27/108 , G11C11/34 , H01L21/84 , H01L27/115 , H01L27/12
CPC分类号： H01L27/1225 , H01L21/84 , H01L27/088 , H01L27/108 , H01L27/1156 , H01L27/1203 , H01L27/1222 , H01L27/1251
摘要： A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.
摘要翻译：提供在绝缘区域上方设置有在第一半导体区域和第二半导体区域上设置绝缘区域的衬底上的第一场效应晶体管; 设置在所述基板上的绝缘层; 第二场效应晶体管，其设置在所述绝缘层的一个平面上，并且包括氧化物半导体层; 并提供控制终端。控制端子以与第二场效应晶体管的源极和漏极相同的步骤形成，并且用于控制第一场效应晶体管的阈值电压的电压被提供给控制端子。

5. 发明授权

US08036604B2 Transmitting and receiving circuit and semiconductor device including the same 有权
标题翻译：发射和接收电路和包括其的半导体器件
公开(公告)号：US08036604B2
公开(公告)日：2011-10-11
申请号：US12003112
申请日：2007-12-20
申请人： Masashi Fujita , Yutaka Shionoiri
发明人： Masashi Fujita , Yutaka Shionoiri
IPC分类号： H04B1/38
CPC分类号： H03F1/56 , H03F1/0205 , H03F3/245 , H03F2200/327
摘要： An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.
摘要翻译：目的在于提供一种在发送和接收电路中可以减少晶体管数量并且可以防止功率转换效率降低的电路配置。发送和接收电路包括具有N级的倍压整流电路，每个级包括电容器，其中N是正整数。具有N级的倍压整流电路连接到具有调制功能的电路。在N级中的任何一级的电容器中，一个电容器的一个电极连接到发送和接收电路的输入端子，并且连接一个电容器的另一个电极的节点连接到具有解调功能。由于发送和接收电路可以由更少的晶体管形成，所以可以减小其尺寸。由于可以防止功率转换效率的降低，所以可以有效地产生电源电位。

6. 发明申请

US20080149738A1 Transmitting and receiving circuit and semiconductor device including the same 有权
标题翻译：发射和接收电路和包括其的半导体器件
公开(公告)号：US20080149738A1
公开(公告)日：2008-06-26
申请号：US12003112
申请日：2007-12-20
申请人： Masashi Fujita , Yutaka Shionoiri
发明人： Masashi Fujita , Yutaka Shionoiri
IPC分类号： G06K19/06
CPC分类号： H03F1/56 , H03F1/0205 , H03F3/245 , H03F2200/327
摘要： An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.
摘要翻译：目的在于提供一种在发送和接收电路中可以减少晶体管数量并且可以防止功率转换效率降低的电路配置。发送和接收电路包括具有N级的倍压整流电路，每个级包括电容器，其中N是正整数。具有N级的倍压整流电路连接到具有调制功能的电路。在N级中的任何一级的电容器中，一个电容器的一个电极连接到发送和接收电路的输入端子，并且连接一个电容器的另一个电极的节点连接到具有解调功能。由于发送和接收电路可以由更少的晶体管形成，所以可以减小其尺寸。由于可以防止功率转换效率的降低，所以可以有效地产生电源电位。

7. 发明申请

US20120287703A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120287703A1
公开(公告)日：2012-11-15
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/24
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

8. 发明授权

US08817527B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08817527B2
公开(公告)日：2014-08-26
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/00 , G06F12/08
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

9. 发明申请

US20080247208A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20080247208A1
公开(公告)日：2008-10-09
申请号：US12051473
申请日：2008-03-19
申请人： Masashi Fujita , Kiyoshi Kato
发明人： Masashi Fujita , Kiyoshi Kato
IPC分类号： H02M7/217
CPC分类号： G06K19/0723 , G06K19/0701
摘要： A semiconductor device is provided, which comprises a rectifier circuit configured to generate a first voltage from a first signal inputted from an input terminal, a comparing circuit configured to compare a reference voltage and the first voltage inputted from the rectifier circuit and to output a second signal to a switch, and a voltage generation circuit configured to generate a second voltage from the first signal inputted from the input terminal. The rectifier circuit includes a transistor including at least a control terminal, and the voltage generation circuit inputs the second voltage to the control terminal when the switch is turned on in accordance with the second signal.
摘要翻译：提供一种半导体器件，其包括：整流电路，被配置为根据从输入端子输入的第一信号产生第一电压;比较电路，被配置为比较参考电压和从整流器电路输入的第一电压，并输出第二电压信号到开关，以及电压产生电路，被配置为根据从输入端子输入的第一信号产生第二电压。整流电路包括至少包括控制端子的晶体管，并且当根据第二信号接通开关时，电压产生电路将第二电压输入到控制端子。

10. 发明授权

US08164933B2 Power source circuit 有权
标题翻译：电源电路
公开(公告)号：US08164933B2
公开(公告)日：2012-04-24
申请号：US12051473
申请日：2008-03-19
申请人： Masashi Fujita , Kiyoshi Kato
发明人： Masashi Fujita , Kiyoshi Kato
IPC分类号： H02M7/217
CPC分类号： G06K19/0723 , G06K19/0701
摘要： A semiconductor device is provided, which comprises a rectifier circuit configured to generate a first voltage from a first signal inputted from an input terminal, a comparing circuit configured to compare a reference voltage and the first voltage inputted from the rectifier circuit and to output a second signal to a switch, and a voltage generation circuit configured to generate a second voltage from the first signal inputted from the input terminal. The rectifier circuit includes a transistor including at least a control terminal, and the voltage generation circuit inputs the second voltage to the control terminal when the switch is turned on in accordance with the second signal.
摘要翻译：提供一种半导体器件，其包括：整流电路，被配置为根据从输入端子输入的第一信号产生第一电压;比较电路，被配置为比较参考电压和从整流器电路输入的第一电压，并输出第二电压信号到开关，以及电压产生电路，被配置为根据从输入端子输入的第一信号产生第二电压。整流电路包括至少包括控制端子的晶体管，并且当根据第二信号接通开关时，电压产生电路将第二电压输入到控制端子。

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