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1. 发明申请

US20120293201A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120293201A1
公开(公告)日：2012-11-22
申请号：US13469143
申请日：2012-05-11
申请人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
发明人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17772 , H03K19/17776
摘要： An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.
摘要翻译：目的是提供即使在电源电压停止之后也能够维持逻辑电路单元之间的连接关系或每个逻辑电路单元的电路配置的半导体器件。另一个目的是提供一种半导体器件，其中可以高速地改变逻辑电路单元之间的连接关系或每个逻辑电路单元的电路配置。在可重构电路中，氧化物半导体用于存储关于电路配置，连接关系等的数据的半导体元件。具体地，氧化物半导体用于半导体元件的沟道形成区域。

2. 发明授权

US09762246B2 Semiconductor device with a storage circuit having an oxide semiconductor 有权
公开(公告)号：US09762246B2
公开(公告)日：2017-09-12
申请号：US13469143
申请日：2012-05-11
申请人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
发明人： Masashi Fujita , Yutaka Shionoiri , Kiyoshi Kato , Hidetomo Kobayashi
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17772 , H03K19/17776
摘要： An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

3. 发明授权

US09123581B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09123581B2
公开(公告)日：2015-09-01
申请号：US13287569
申请日：2011-11-02
申请人： Toshihiko Saito , Yutaka Shionoiri , Kiyoshi Kato
发明人： Toshihiko Saito , Yutaka Shionoiri , Kiyoshi Kato
IPC分类号： G06K19/06 , H01L27/12 , G06K19/07 , H01L21/84
CPC分类号： H01L27/12 , G06K19/0701 , G06K19/0715 , G06K19/0723 , H01L21/84
摘要： An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.
摘要翻译：本发明的目的是提供一种使用小电路区域可以获得将数据写入存储器所需的高电位的半导体器件。在本发明中，通过使用升压电路的输入电压而不是调节器电路104的常规使用的输出VDD，而是使用比VDD高的电压的整流电路部分103的输出VDD0，可以以小的电路面积获得将数据写入存储器所必需的。

4. 发明申请

US20120133437A1 SENSE AMPLIFIER AND ELECTRONIC APPARATUS USING THE SAME 有权
标题翻译：使用相同的感应放大器和电子设备
公开(公告)号：US20120133437A1
公开(公告)日：2012-05-31
申请号：US13367397
申请日：2012-02-07
申请人： Yutaka Shionoiri , Kiyoshi Kato , Munehiro Azami
发明人： Yutaka Shionoiri , Kiyoshi Kato , Munehiro Azami
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , G01R19/00 , G11C7/062 , G11C11/4091 , G11C11/413 , G11C2207/063 , H03F3/45183 , H03F3/45188 , H03F2203/45396 , H03F2203/45506 , H03F2203/45546 , H03F2203/45551 , H03F2203/45702 , H03F2203/45726
摘要： A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
摘要翻译：根据本发明的用于检测输入到第一输入端和第二输入端的信号的电位差的读出放大器包括：第一装置，用于将对应于第一和第二晶体管的阈值电压的电压施加到栅极源电压第一和第二晶体管，以及用于将输入到第一和第二输入端的信号传送到第一和第二晶体管的栅极的第二装置。在这种情况下，校正第一和第二晶体管的阈值变化。

5. 发明申请

US20110175083A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110175083A1
公开(公告)日：2011-07-21
申请号：US13004200
申请日：2011-01-11
申请人： Yusuke Sekine , Yutaka Shionoiri , Kiyoshi Kato , Shunpei Yamazaki
发明人： Yusuke Sekine , Yutaka Shionoiri , Kiyoshi Kato , Shunpei Yamazaki
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A semiconductor device has a non-volatile memory cell including a write transistor which includes an oxide semiconductor and has small leakage current in an off state (off-state current) between a source and a drain, a read transistor including a semiconductor material different from that of the write transistor, and a capacitor. Data is written or to the memory cell by applying a potential to a node where one of a source electrode and drain electrode of the write transistor, one electrode of the capacitor, and a gate electrode of the read transistor are electrically connected to one another so that the predetermined amount of charge is held in the node. The memory window width is changed by 2% or less, before and after 1×109 times of writing.
摘要翻译：半导体器件具有包括写入晶体管的非易失性存储单元，该晶体管包括氧化物半导体，并且在源极和漏极之间的截止状态（截止状态电流）中具有小的漏电流，读取晶体管包括不同于写晶体管和电容器。通过向写入晶体管的源电极和漏电极，电容器的一个电极和读取晶体管的栅电极之一彼此电连接的节点施加电位而将数据写入或存储到存储器单元，从而在节点中保持预定量的电荷。 1×109次写入之前和之后，存储窗宽度改变2％以下。

6. 发明申请

US20090289340A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090289340A1
公开(公告)日：2009-11-26
申请号：US12468280
申请日：2009-05-19
申请人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
发明人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
IPC分类号： H01L23/02 , H01L21/56
CPC分类号： G06K19/07749 , G06K19/07735 , H01L27/1214 , H01L27/1218 , H01L27/1266 , H01L27/13 , H01Q1/2225 , H01Q1/2283 , H01Q1/526 , H01Q7/00
摘要： A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown of the semiconductor integrated circuit (e.g., malfunction of a circuit and damage to a semiconductor element) due to electrostatic discharge. Further, with use of a pair of insulators between which the semiconductor integrated circuit is sandwiched, a highly reliable semiconductor having resistance can be provided while achieving reduction in the thickness and size. Moreover, also in the manufacturing process, external stress, or defective shapes or deterioration in characteristics resulted from electrostatic discharge are prevented, and thus the semiconductor device can be manufactured with high yield.
摘要翻译：覆盖半导体集成电路的导电屏蔽防止由于静电放电而导致的半导体集成电路的静电破坏（例如，电路的故障和对半导体元件的损坏）。此外，通过使用夹在半导体集成电路之间的一对绝缘体，可以提供具有电阻的高可靠性的半导体，同时实现厚度和尺寸的减小。此外，在制造过程中也防止外部应力或形状不良或由静电放电导致的特性劣化，从而可以高产率制造半导体器件。

7. 发明授权

US07352604B2 Memory and driving method of the same 有权
标题翻译：内存和驱动方法相同
公开(公告)号：US07352604B2
公开(公告)日：2008-04-01
申请号：US11607053
申请日：2006-12-01
申请人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
发明人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
IPC分类号： G11C17/00
CPC分类号： G11C7/1096 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C17/12
摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.
摘要翻译：根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。时钟反相器的输入节点连接到位线，而输出节点连接到数据线。在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极源极或漏极连接到低电位侧的电源VSS连接到列解码器。

8. 发明申请

US20060255837A1 Sense Amplifier and Electronic Apparatus Using the Same 有权
公开(公告)号：US20060255837A1
公开(公告)日：2006-11-16
申请号：US11458710
申请日：2006-07-20
申请人： Yutaka Shionoiri , Kiyoshi Kato , Munehiro Azami , Junya Maruyama
发明人： Yutaka Shionoiri , Kiyoshi Kato , Munehiro Azami , Junya Maruyama
IPC分类号： G01R19/00
CPC分类号： H03F3/45179 , G01R19/00 , G11C7/062 , G11C11/4091 , G11C11/413 , G11C2207/063 , H03F3/45183 , H03F3/45188 , H03F2203/45396 , H03F2203/45506 , H03F2203/45546 , H03F2203/45551 , H03F2203/45702 , H03F2203/45726
摘要： A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

9. 发明申请

US20050273290A1 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US20050273290A1
公开(公告)日：2005-12-08
申请号：US11132434
申请日：2005-05-19
申请人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
发明人： Etsuko Asano , Kiyoshi Kato , Yutaka Shionoiri , Masahiko Hayakawa
IPC分类号： G01R31/317 , G01R31/3187 , G06F19/00
CPC分类号： G01R31/3187 , G01R31/31723 , G01R31/31725 , G01R31/31726
摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.
摘要翻译：本发明提供了一种用于评估预期元素或参数的方法。此外，本发明提供了一种快速获得更精确结果的评估方法。根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

10. 发明申请

US20050029519A1 TV set and digital camera 有权
标题翻译：电视机和数码相机
公开(公告)号：US20050029519A1
公开(公告)日：2005-02-10
申请号：US10941823
申请日：2004-09-16
申请人： Shunpei Yamazaki , Kiyoshi Kato , Atsuo Isobe , Hidekazu Miyairi , Hideomi Suzawa , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shunpei Yamazaki , Kiyoshi Kato , Atsuo Isobe , Hidekazu Miyairi , Hideomi Suzawa , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/04
CPC分类号： H01L21/02609 , H01L21/2026 , H01L27/12 , H01L27/1281 , H01L29/66757 , H01L29/78621 , H01L29/78675 , H01L29/78696
摘要： A semiconductor element which is capable of operating at a high speed, high in an electric current drive capability, and small in fluctuation among a plurality of elements, and a semiconductor device including the semiconductor element are provided. The semiconductor element has a first crystalline semiconductor region including plural crystal orientations without practically having a grain boundary on an insulating surface, the first crystalline semiconductor region being provided to be jointly connected to a conductive region including the first crystalline semiconductor region and a second crystalline semiconductor region, in which the conductive region is provided astride insulating films extending in a linear stripe pattern.
摘要翻译：提供能够高速运行，电流驱动能力高，多个元件之间波动小的半导体元件，以及包括半导体元件的半导体器件。半导体元件具有包括多个晶体取向的第一晶体半导体区域，而绝缘表面实际上不具有晶界，第一晶体半导体区域被设置为共同连接到包括第一晶体半导体区域的导电区域和第二晶体半导体区域区域，其中导电区域被设置成跨过线性条纹图案延伸的绝缘膜。

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