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1. 发明申请

US20100313176A1 DELAY LIBRARY, DELAY LIBRARY CREATION METHOD, AND DELAY CALCULATION METHOD 审中-公开
标题翻译：延迟图书馆，延迟图书馆创作方法和延迟计算方法
公开(公告)号：US20100313176A1
公开(公告)日：2010-12-09
申请号：US12743965
申请日：2009-02-24
申请人： Masao Takahashi , Kazuhiro Satoh , Noriko Ishibashi , Naoki Amekawa
发明人： Masao Takahashi , Kazuhiro Satoh , Noriko Ishibashi , Naoki Amekawa
IPC分类号： G06F9/455
CPC分类号： G06F17/5031
摘要： A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based on a signal transition timing in each of the input terminals. An overlap between the timing windows (TW) of input signals is detected, and a circuit delay time is calculated by selectively using one of a synchronous transition time and an asynchronous transition time in accordance with the overlap between the timing windows (TW). These processing steps are sequentially repeated to eliminate an optimistic or pessimistic analysis in the calculation of delay times in the multi-input logic cell.
摘要翻译：基于每个输入端子中的信号转换时序，为多输入逻辑单元中的输入端子中的每个输入信号产生表示在时间轴中可能发生信号转换的时区的定时窗口（TW）。检测输入信号的定时窗口（TW）之间的重叠，并且通过根据时序窗口（TW）之间的重叠选择性地使用同步转换时间和异步转换时间之一来计算电路延迟时间。顺序地重复这些处理步骤，以消除在多输入逻辑单元中的延迟时间的计算中的乐观或悲观的分析。

2. 发明申请

US20050256921A1 Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method 审中-公开
标题翻译：延迟计算方法，时序分析法，计算对象网络近似法，延迟控制法等
公开(公告)号：US20050256921A1
公开(公告)日：2005-11-17
申请号：US10891496
申请日：2004-07-15
申请人： Naoki Amekawa , Takahiro Ichinomiya , Kazuhiro Satoh
发明人： Naoki Amekawa , Takahiro Ichinomiya , Kazuhiro Satoh
IPC分类号： G06F17/50 , G06G7/00 , H01L21/82 , H01L27/04 , H03K5/14
CPC分类号： G06F17/5036
摘要： A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.
摘要翻译：考虑与半导体集成电路的延迟计算对象网相邻的网络的延迟计算方法包括：相邻的网络内部电阻选择步骤，选择相邻网络驱动单元的静态的组合; 耦合电容接地步骤，将耦合电容乘以由相邻的净内部电阻选择步骤选择的相邻净驱动单元的内部电阻获得的系数等，并将由此获得的值接地作为延迟计算物体网; 以及延迟值导出步骤，从通过这些步骤获得的电路导出延迟值。通过这种结构解决了实际上电位波动近似为零电位的相邻导线的滞后计算方法不能获得精确延迟值的问题。

3. 发明授权

US06988254B2 Method for designing semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法
公开(公告)号：US06988254B2
公开(公告)日：2006-01-17
申请号：US10601287
申请日：2003-06-20
申请人： Nobufusa Iwanishi , Kazuhiro Satoh , Noriko Ishibashi
发明人： Nobufusa Iwanishi , Kazuhiro Satoh , Noriko Ishibashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其能够通过在不减少元件排列所需的有效面积的情况下减少IR降低对定时的影响而实现近似于实际操作的定时仿真或者焊盘的数量可以使用电源垫以外的处理时间。在FF驱动能力改变过程中，具有大于从电源电压中的IR降低到理想电源电压的状态的转变时间的延迟时间的触发器被替换为任意翻转 -flop。因此，考虑到IR降低的延迟库可以仅在触发器中产生，从而能够减少库的生产时间并提高延迟计算过程中的延迟时间的计算精度。此外，替代具有低驾驶能力的触发器使得能够减小面积。

4. 发明授权

US06938233B2 Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution 失效
标题翻译：基于电压降分布设计半导体集成电路器件的方法和装置
公开(公告)号：US06938233B2
公开(公告)日：2005-08-30
申请号：US10637254
申请日：2003-08-08
申请人： Kazuhiro Satoh , Nobufusa Iwanishi , Noriko Ishibashi
发明人： Kazuhiro Satoh , Nobufusa Iwanishi , Noriko Ishibashi
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5068
摘要： A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of carrying out a schematic arrangement so as to minimize a distance of a wiring for connecting between the transistors or wiring capacitance based on input information on transistors; a second step of producing information on a voltage drop value based on the schematic arrangement of the transistors; and a third step of arranging the transistors based on the information on a voltage drop value.
摘要翻译：一种半导体集成电路器件的设计方法，用于通过金属布线连接在硅晶片上形成的晶体管的端子之间。该方法包括执行示意性布置的第一步骤，以便基于晶体管上的输入信息来最小化用于连接晶体管或布线电容的布线的距离; 基于晶体管的示意性布置产生关于电压降值的信息的第二步骤; 以及基于关于电压降值的信息来布置晶体管的第三步骤。

5. 发明授权

US06810724B2 Engine reversing detection system for outboard motor 有权
标题翻译：舷外马达发动机反向检测系统
公开(公告)号：US06810724B2
公开(公告)日：2004-11-02
申请号：US10267829
申请日：2002-10-10
申请人： Ryuichi Kimata , Kazuhiro Satoh , Nobuhiro Takahashi
发明人： Ryuichi Kimata , Kazuhiro Satoh , Nobuhiro Takahashi
IPC分类号： G01M1500
CPC分类号： F02P7/067 , F02B61/045 , F02D41/009 , F02D2041/0092 , F02D2250/06 , G01P13/04
摘要： A system for detecting reverse rotation of a 4-cycle, internal combustion engine with three or more cylinder for an outboard motor mounted on a boat, whose output is connected to a propeller such that the boat is propelled forward or reverse. In the system, it is determined whether a counted value of crank angle signals generated once every 30 crank angles is a multiple of a predetermined number (e.g., four in six cylinders), when the cylinders are identified and it is determined that engine rotates reverse when the counted value is determined to be not the multiple and the engine is immediately stopped. With this, it becomes possible to accurately detect the reverse rotation of the engine and prevent its further reverse rotation.
摘要翻译：用于检测安装在船上的舷外马达的具有三个或更多个气缸的四循环内燃机的反向旋转的系统，其输出连接到螺旋桨，使得船向前或向后推进。在该系统中，确定每30个曲柄角一次产生的曲柄角度信号的计数值是否为预定数量的倍数（例如，六个气缸中的四个），当确定气缸时，确定发动机反转当计数值被确定为不是倍数且发动机立即停止时。由此，可以精确地检测发动机的反转，防止其进一步反转。

6. 发明授权

US06792797B2 Engine malfunction detection system 失效
标题翻译：发动机故障检测系统
公开(公告)号：US06792797B2
公开(公告)日：2004-09-21
申请号：US10267992
申请日：2002-10-10
申请人： Kazuhiro Satoh , Nobuhiro Takahashi
发明人： Kazuhiro Satoh , Nobuhiro Takahashi
IPC分类号： G01M1900
CPC分类号： F02D41/22 , F02D41/222 , Y02T10/40
摘要： A system for detecting malfunction of an equipment such as an alternator or a hydraulic switch that is connected to an internal combustion engine and generates an output. In the system, it is discriminated periodically for a predetermined period of time whether the output of the equipment is within a predetermined range, a number of times that the output of the equipment is discriminated to be out of the predetermined range is counted; and the equipment is determined to have malfunctioned when the count is equal to or greater than the reference value. With this, it becomes possible to detect the malfunction of the equipment accurately.
摘要翻译：一种用于检测连接到内燃机并且产生输出的诸如交流发电机或液压开关的设备的故障的系统。在该系统中，对于设备的输出是否在规定的范围内，周期性地进行判别，将设备的输出判别为规定范围以外的次数进行计数; 当计数等于或大于参考值时，设备被确定为发生故障。由此，可以准确地检测设备的故障。

7. 发明授权

US06708318B2 Wiring resistance correcting method 有权
标题翻译：接线电阻校正方法
公开(公告)号：US06708318B2
公开(公告)日：2004-03-16
申请号：US09963563
申请日：2001-09-27
申请人： Kazuhiro Satoh , Fumihiro Kimura
发明人： Kazuhiro Satoh , Fumihiro Kimura
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Where there are wirings with different film thicknesses or a sheet resistance in a non-scraped state of a wiring layer cannot be obtained as a result of the CPM technique, a wiring resistance according to a film thickness when an LSI is manufactured is acquired by automatic processing to reduce its difference from a real resistance, and accurate voltage drop analysis is carried out to reduce malfunction in a real chip. In a semiconductor circuit device with a plurality of kinds of film thicknesses in the same wiring layer, with a variation occurring in the wiring film thickness when wirings are formed on a silicon wafer, or a warp occurring in an upper layer because the stacking of lower layers is not uniform in the manufacturing process of the wiring, an error of the wiring resistance due to the difference in the film thickness or warp of the wiring is corrected to produce a virtual layout data.
摘要翻译：在采用CPM技术的情况下，由于不能获得具有不同膜厚度的布线或布线层的无刮擦状态的薄层电阻，因此通过自动获取当制造LSI时根据膜厚度的布线电阻处理以减少与实际电阻的差异，并进行精确的电压降分析以减少真实芯片中的故障。在同一布线层中具有多种膜厚的半导体电路器件中，当在硅晶片上形成布线时发生在布线膜厚度上的变化，或由于下层叠层而产生的翘曲在布线的制造过程中层数不均匀，校正了由于膜厚度的差异或布线翘曲引起的布线电阻的误差，从而产生虚拟布局数据。

8. 发明授权

US06374052B1 Camera 失效
标题翻译：相机
公开(公告)号：US06374052B1
公开(公告)日：2002-04-16
申请号：US09621362
申请日：2000-07-21
申请人： Kazuhiro Satoh , Hirohide Fukazawa , Akira Kasai , Kazuo Akai , Nobuharu Namikawa , Jun Inoue
发明人： Kazuhiro Satoh , Hirohide Fukazawa , Akira Kasai , Kazuo Akai , Nobuharu Namikawa , Jun Inoue
IPC分类号： G03B1700
CPC分类号： G03B17/02
摘要： To provide a camera configured to be supported by the hands of a photographer on the bottom surface of the body thereof whose operability is improved by allowing various settings to be easily made with the camera body supported reliably and allowing a set value to be stored and retrieved with a small number of operation members, a configuration is provided which includes a grip portion protruding in a direction orthogonal to an optical axis of a photographic optical system provided in a predetermined position of a lateral surface of the body of the camera and an operating member for allowing input of information to cause execution of a predetermined operation, the operating member being provided in the vicinity of the grip portion. There is further provided a setting member for setting a desired set value, a set value storing member for storing data representing desired set values which can be set with the setting member in advance, a set value retrieving member for arbitrarily reading the data stored in advance with the set value storing member instead of the set value set with the setting member and for setting a set value based on the same and control unit for controlling the set value storing member and the set value retrieving member such that they can be operated with a single operating member.
摘要翻译：为了提供一种照相机，其配置为通过允许可靠地支持相机机身容易地进行各种设置并且允许存储和检索设定值的本体的底表面上的摄影者的手来支持其可操作性，具有少量的操作构件，提供了一种构造，其包括沿与垂直于设置在照相机的主体的侧表面的预定位置的照相光学系统的光轴方向突出的把手部分和操作构件为了允许输入信息以执行预定的操作，操作构件设置在把手部分附近。还设置有用于设定所需设定值的设定部件，设定值存储部件，用于存储表示预先设定的设定部件所期望的设定值的数据，设定值检索部件，用于任意读取预先存储的数据设定值存储部件而不是设定部件设定的设定值，并且基于相同的设定值和用于控制设定值存储部件和设定值检索部件的控制部，使得能够以单操作员。

9. 发明授权

US06272028B1 Power converter apparatus 有权
标题翻译：电力转换装置
公开(公告)号：US06272028B1
公开(公告)日：2001-08-07
申请号：US09649001
申请日：2000-08-28
申请人： Kazuhiro Satoh , Ryo Nakajima , Kosaku Ichikawa
发明人： Kazuhiro Satoh , Ryo Nakajima , Kosaku Ichikawa
IPC分类号： H02H7122
CPC分类号： H02M7/48 , H02M1/12
摘要： A power converter apparatus, including a DC power source, a semiconductor stack, connected to the DC power source in parallel, having a plurality of semiconductor devices and a cooler for refrigerating the semiconductor devices, the semiconductor devices and the cooler are stacked and pressured to each other, and a snubber circuit, connected to the DC power source in parallel, having a serial circuit of a capacitor and a diode, and a resistor connected in parallel to the diode, one terminal of the capacitor is disposed adjacent to the semiconductor stack so that magnetic flux generated by current flowing in the terminal cancels magnetic flux caused by current flowing in the semiconductor stack.
摘要翻译：并联连接到具有多个半导体器件的DC电源的DC电源，半导体堆叠以及用于将半导体器件，半导体器件和冷却器冷却的冷却器的功率转换器装置被堆叠并加压到彼此连接的并联连接到DC电源的缓冲电路，具有电容器和二极管的串联电路以及与二极管并联连接的电阻器，电容器的一个端子邻近半导体堆叠设置使得在端子中流动的电流产生的磁通消除由在半导体堆叠中流动的电流引起的磁通量。

10. 发明授权

US5825992A Facsimile device 失效
标题翻译：传真机
公开(公告)号：US5825992A
公开(公告)日：1998-10-20
申请号：US658441
申请日：1996-06-10
申请人： Kazuhiro Satoh
发明人： Kazuhiro Satoh
IPC分类号： H04N1/32
CPC分类号： H04N1/32379 , H04N1/32363 , H04N1/32496 , H04N2201/3298
摘要： A facsimile device operable in either a memory receiving mode or direct receiving mode. When the device is put in a memory receiving mode after previous memory receiving, the image information transmitted next time is directly received, and thereby the repetition of the memory receiving mode and the retransmission of information can be eliminated and the convenience of memory receiving can be improved. A facsimile control portion detects a memory remaining amount of the image information memory available storing image information. When the absence of a memory remaining amount is detected, the occurrence of a memory over (operation in the memory receiving mode) is stored in the system memory. When the calling arrival occurs, the document is memory-received or directly received on the basis of the presence or absence of the memory over occurrence stored in the system memory.
摘要翻译：一种可在存储器接收模式或直接接收模式下操作的传真装置。当在先前的存储器接收之后将设备置于存储器接收模式时，直接接收下一次发送的图像信息，从而可以消除存储器接收模式的重复和信息的重传，并且可以方便地进行存储器接收改进。传真控制部分检测可用的图像信息存储器的存储器剩余量存储图像信息。当检测到没有存储器剩余量时，存储器的发生（存储器接收模式中的操作）被存储在系统存储器中。当呼叫到达发生时，根据存储在系统存储器中的存在的存在或不存在，文档被存储器接收或直接接收。

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