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1. 发明授权

US06988254B2 Method for designing semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法
公开(公告)号：US06988254B2
公开(公告)日：2006-01-17
申请号：US10601287
申请日：2003-06-20
申请人： Nobufusa Iwanishi , Kazuhiro Satoh , Noriko Ishibashi
发明人： Nobufusa Iwanishi , Kazuhiro Satoh , Noriko Ishibashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其能够通过在不减少元件排列所需的有效面积的情况下减少IR降低对定时的影响而实现近似于实际操作的定时仿真或者焊盘的数量可以使用电源垫以外的处理时间。在FF驱动能力改变过程中，具有大于从电源电压中的IR降低到理想电源电压的状态的转变时间的延迟时间的触发器被替换为任意翻转 -flop。因此，考虑到IR降低的延迟库可以仅在触发器中产生，从而能够减少库的生产时间并提高延迟计算过程中的延迟时间的计算精度。此外，替代具有低驾驶能力的触发器使得能够减小面积。

2. 发明授权

US06938233B2 Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution 失效
标题翻译：基于电压降分布设计半导体集成电路器件的方法和装置
公开(公告)号：US06938233B2
公开(公告)日：2005-08-30
申请号：US10637254
申请日：2003-08-08
申请人： Kazuhiro Satoh , Nobufusa Iwanishi , Noriko Ishibashi
发明人： Kazuhiro Satoh , Nobufusa Iwanishi , Noriko Ishibashi
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5068
摘要： A method for designing a semiconductor integrated circuit device for connecting between terminals of transistors formed on a silicon wafer by metal wiring. The method includes a first step of carrying out a schematic arrangement so as to minimize a distance of a wiring for connecting between the transistors or wiring capacitance based on input information on transistors; a second step of producing information on a voltage drop value based on the schematic arrangement of the transistors; and a third step of arranging the transistors based on the information on a voltage drop value.
摘要翻译：一种半导体集成电路器件的设计方法，用于通过金属布线连接在硅晶片上形成的晶体管的端子之间。该方法包括执行示意性布置的第一步骤，以便基于晶体管上的输入信息来最小化用于连接晶体管或布线电容的布线的距离; 基于晶体管的示意性布置产生关于电压降值的信息的第二步骤; 以及基于关于电压降值的信息来布置晶体管的第三步骤。

3. 发明授权

US07925998B2 Delay calculating method in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的延迟计算方法
公开(公告)号：US07925998B2
公开(公告)日：2011-04-12
申请号：US11296640
申请日：2005-12-08
申请人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
摘要翻译：在功能表达式中预先获得单元的输入引脚电容，并且以这样的方式计算延迟，使得在每种情况下以输入转换和驱动负载电容的功能计算输入引脚电容。在单元特征处理中，获得在输入端子的电压值达到基准电压之前进入输入端子的电流的总体积，从而可以获得接近实际输入引脚电容的值。

4. 发明申请

US20050232066A1 Method for characterizing cells with consideration for bumped waveform and delay time calculation method for semiconductor integrated circuits using the same 审中-公开
标题翻译：考虑使用其的半导体集成电路的凸起波形和延迟时间计算方法来表征单元的方法
公开(公告)号：US20050232066A1
公开(公告)日：2005-10-20
申请号：US11108696
申请日：2005-04-19
申请人： Noriko Ishibashi , Naoki Amekawa , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Naoki Amekawa , Nobufusa Iwanishi
IPC分类号： G06F17/50 , G11C8/00
CPC分类号： G06F17/5036
摘要： An effective input terminal capacitance which is effectively equivalent to a cell in which a waveform distortion is caused due to the Miller effect and a drive load connected to the cell is calculated in advance, and the cell and the drive load are replaced by the calculated effective input terminal capacitance, while considering that the Miller effect is caused according to the size of the drive load driven by a delay time calculation subject circuit, such as a cell, or the like, and a distortion occurs in input and output waveforms of the delay time calculation subject circuit due to the Miller effect. Thereafter, a circuit simulation is carried out using the effective input terminal capacitance. A resultant effective input terminal capacitance value is characterized as a function of an input slope waveform and the drive load and converted to table data.
摘要翻译：预先计算有效输入端子电容，其有效地等效于由于米勒效应引起的波形失真的单元和连接到单元的驱动负载的单元，并且计算单元和驱动负载被计算的有效输入端子电容，同时考虑到由延迟时间计算对象电路（例如单元等）驱动的驱动负载的大小引起米勒效应，并且在延迟的输入和输出波形中发生失真时间计算主题电路由于米勒效应。此后，使用有效输入端子电容进行电路仿真。合成的有效输入端电容值的特征在于输入斜率波形和驱动负载的函数，并转换为表数据。

5. 发明申请

US20070300196A1 Delay calculating method in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中的延迟计算方法
公开(公告)号：US20070300196A1
公开(公告)日：2007-12-27
申请号：US11296640
申请日：2005-12-08
申请人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
发明人： Noriko Ishibashi , Masaaki Hirata , Nobufusa Iwanishi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell characterizing process, a total volume of a current running into an input terminal before a voltage value of the input terminal reaches a reference voltage is obtained so that a value approximate to a real input pin capacitance can be obtained.
摘要翻译：在功能表达式中预先获得单元的输入引脚电容，并且以这样的方式计算延迟，使得在每种情况下以输入转换和驱动负载电容的功能计算输入引脚电容。在单元特征处理中，获得在输入端子的电压值达到基准电压之前进入输入端子的电流的总体积，从而可以获得接近实际输入引脚电容的值。

6. 发明申请

US20100313176A1 DELAY LIBRARY, DELAY LIBRARY CREATION METHOD, AND DELAY CALCULATION METHOD 审中-公开
标题翻译：延迟图书馆，延迟图书馆创作方法和延迟计算方法
公开(公告)号：US20100313176A1
公开(公告)日：2010-12-09
申请号：US12743965
申请日：2009-02-24
申请人： Masao Takahashi , Kazuhiro Satoh , Noriko Ishibashi , Naoki Amekawa
发明人： Masao Takahashi , Kazuhiro Satoh , Noriko Ishibashi , Naoki Amekawa
IPC分类号： G06F9/455
CPC分类号： G06F17/5031
摘要： A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based on a signal transition timing in each of the input terminals. An overlap between the timing windows (TW) of input signals is detected, and a circuit delay time is calculated by selectively using one of a synchronous transition time and an asynchronous transition time in accordance with the overlap between the timing windows (TW). These processing steps are sequentially repeated to eliminate an optimistic or pessimistic analysis in the calculation of delay times in the multi-input logic cell.
摘要翻译：基于每个输入端子中的信号转换时序，为多输入逻辑单元中的输入端子中的每个输入信号产生表示在时间轴中可能发生信号转换的时区的定时窗口（TW）。检测输入信号的定时窗口（TW）之间的重叠，并且通过根据时序窗口（TW）之间的重叠选择性地使用同步转换时间和异步转换时间之一来计算电路延迟时间。顺序地重复这些处理步骤，以消除在多输入逻辑单元中的延迟时间的计算中的乐观或悲观的分析。

7. 发明授权

US06336205B1 Method for designing semiconductor integrated circuit 失效
标题翻译：半导体集成电路设计方法
公开(公告)号：US06336205B1
公开(公告)日：2002-01-01
申请号：US09437511
申请日：1999-11-10
申请人： Keiichi Kurokawa , Masahiko Toyonaga , Noriko Ishibashi
发明人： Keiichi Kurokawa , Masahiko Toyonaga , Noriko Ishibashi
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A semiconductor integrated circuit includes: a first register connected to the input of a first group of logic devices; a second register connected between the first and second groups of logic devices; and a third register connected to the output of the second group of logic devices. The integrated circuit is designed in the following manner. First, a shortest one of delays caused by respective signal propagation paths between the first and second registers and a shortest one of delays caused by respective signal propagation paths between the second and third registers are added together to obtain a shortest total delay. Next, if the shortest total delay is longer than a time obtained by subtracting one clock cycle time from a sum of constraint times defining respective signal propagation times between the first and second registers and between the second and third registers, then the second register is removed, thereby connecting the first and second groups of logic devices together.
摘要翻译：半导体集成电路包括：连接到第一组逻辑器件的输入的第一寄存器; 第二寄存器，连接在所述第一和第二逻辑器件组之间; 以及连接到第二组逻辑器件的输出的第三寄存器。集成电路设计如下。首先，将由第一和第二寄存器之间的各个信号传播路径引起的最短延迟和由第二和第三寄存器之间的各个信号传播路径引起的最短延迟相加在一起以获得最短的总延迟。接下来，如果最短的总延迟比通过从限定第一和第二寄存器之间以及第二和第三寄存器之间的各个信号传播时间的约束时间之和减去一个时钟周期时间而获得的时间长，则删除第二寄存器从而将第一和第二组逻辑器件连接在一起。

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