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1. 发明申请

US20130010535A1 NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR OPERATING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT 有权
公开(公告)号：US20130010535A1
公开(公告)日：2013-01-10
申请号：US13619223
申请日：2012-09-14
申请人： Masao SHINGU , Jun FUJIKI , Naoki YASUDA , Koichi MURAOKA
发明人： Masao SHINGU , Jun FUJIKI , Naoki YASUDA , Koichi MURAOKA
IPC分类号： H01L29/792 , G11C11/40
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.

2. 发明申请

US20130234222A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20130234222A1
公开(公告)日：2013-09-12
申请号：US13598748
申请日：2012-08-30
申请人： Naoki YASUDA , Masaaki Higuchi , Katsuyuki Sekine , Masao Shingu
发明人： Naoki YASUDA , Masaaki Higuchi , Katsuyuki Sekine , Masao Shingu
IPC分类号： H01L29/78
CPC分类号： H01L27/11582 , G11C16/0483
摘要： A semiconductor memory device includes a substrate, a structure body, a semiconductor layer, and a memory film. The memory film is provided between the semiconductor layer and the plurality of electrode films. The memory film includes a charge storage film, a block film, and a tunnel film. The block film is provided between the charge storage film and the plurality of electrode films. The tunnel film is provided between the charge storage film and the semiconductor layer. The tunnel film includes a first film containing silicon oxide, a second film containing silicon oxide, and a third film provided between the first film and the second film and containing silicon oxynitride. When a composition of the silicon oxynitride contained in the third film is expressed by a ratio x of silicon oxide and a ratio (1−x) of silicon nitride, 0.5≦x
摘要翻译：半导体存储器件包括衬底，结构体，半导体层和存储膜。存储膜设置在半导体层和多个电极膜之间。存储膜包括电荷存储膜，块膜和隧道膜。阻挡膜设置在电荷存储膜和多个电极膜之间。隧道膜设置在电荷存储膜和半导体层之间。隧道膜包括含有氧化硅的第一膜，含有氧化硅的第二膜和设置在第一膜和第二膜之间并含有氮氧化硅的第三膜。当第三膜中所含的氮氧化硅的组成由氧化硅的比率x和氮化硅的比例（1-x）表示时，0.5×x≤1。

3. 发明申请

US20070132004A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070132004A1
公开(公告)日：2007-06-14
申请号：US11548914
申请日：2006-10-12
申请人： Naoki YASUDA , Yukie NISHIKAWA , Koichi MURAOKA
发明人： Naoki YASUDA , Yukie NISHIKAWA , Koichi MURAOKA
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/4234 , H01L29/513 , H01L29/7881 , H01L29/792
摘要： A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.
摘要翻译：根据本发明实施例的非易失性半导体存储器件包括源极/漏极扩散层，源极/漏极扩散层之间的沟道上的第一绝缘膜，第一绝缘膜上的浮置栅电极和由第一导电层，在浮栅电极上的第二绝缘膜，以及在第二绝缘膜上的控制栅电极。在除了顶层之外的一个第一导电层被定义为第一导电层中的参考层的情况下，参考层的功函数为4.0eV或更大，并且参考层和第一导电层的功函数随着层靠近第二绝缘膜，参考层之上的层逐渐增加。

4. 发明申请

US20120319077A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120319077A1
公开(公告)日：2012-12-20
申请号：US13560557
申请日：2012-07-27
申请人： Naoki YASUDA , Daisuke MATSUSHITA , Koichi MURAOKA
发明人： Naoki YASUDA , Daisuke MATSUSHITA , Koichi MURAOKA
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2418 , H01L27/2481
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of first interconnections arranged parallel, a plurality of second interconnections arranged parallel to intersect the first interconnections, and memory cell portions respectively arranged at intersecting portions between the first and second interconnections and each configured by laminating a variable-resistance element and a diode element. The diode element has a laminated structure having a first insulating film, a conductive fine grain layer and a second insulating film. The physical film thickness of the second insulating film is greater than the first insulating film and the dielectric constant of the second insulating film is greater than the first insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括平行布置的多个第一互连，并行布置成与第一互连相交的多个第二互连，以及分别布置在第一和第二互连之间的相交部分处的每个配置的存储单元部分通过层叠可变电阻元件和二极管元件。二极管元件具有具有第一绝缘膜，导电细晶粒层和第二绝缘膜的层叠结构。第二绝缘膜的物理膜厚度大于第一绝缘膜，并且第二绝缘膜的介电常数大于第一绝缘膜。

5. 发明申请

US20110284944A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20110284944A1
公开(公告)日：2011-11-24
申请号：US13194099
申请日：2011-07-29
申请人： Yasushi NAKASAKI , Koichi MURAOKA , Naoki YASUDA , Shoko KIKUCHI
发明人： Yasushi NAKASAKI , Koichi MURAOKA , Naoki YASUDA , Shoko KIKUCHI
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/513 , H01L29/7881
摘要： A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al2O3.
摘要翻译：一种能够电写入，擦除，读取和保留数据的MONOS型非易失性半导体存储器件，所述存储器件包括源极/漏极区，第一栅极绝缘层，形成在第一栅极绝缘层上的第一电荷俘获层形成在第一电荷俘获层上的第二栅极绝缘层，以及形成在第二栅极绝缘层上的控制电极。第一电荷俘获层包括含有Al和O作为主要元素并且具有由间隙O原子和四价阳离子原子的复合物形成的缺陷对的绝缘膜，代替Al原子，绝缘膜还具有电子未占有的含量从Al2O3的价带最大值测量的2eV-6eV的范围。

6. 发明申请

US20120205735A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120205735A1
公开(公告)日：2012-08-16
申请号：US13404073
申请日：2012-02-24
申请人： Naoki YASUDA , Jun Fujiki
发明人： Naoki YASUDA , Jun Fujiki
IPC分类号： H01L27/115
CPC分类号： H01L21/28282 , H01L27/1157 , H01L29/66833 , H01L29/792
摘要： In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.
摘要翻译：在一个实施例中，提供了一种非易失性半导体存储装置。该装置包括：多个非易失性存储单元。每个非易失性存储单元包括：第一半导体层，包括第一源极区，第一漏极区和第一沟道区; 形成在所述第一沟道区上的块绝缘膜; 形成在所述块绝缘膜上的电荷存储层; 形成在电荷存储层上的隧道绝缘膜; 形成在所述隧道绝缘膜上并且包括第二源极区域，第二漏极区域和第二沟道区域的第二半导体层。第二沟道区形成在隧道绝缘膜上，使得隧道绝缘膜位于第二源区和第二漏区之间。第一沟道区的掺杂剂杂质浓度高于第二沟道区的掺杂剂杂质浓度。

7. 发明申请

US20110254049A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110254049A1
公开(公告)日：2011-10-20
申请号：US13160204
申请日：2011-06-14
申请人： Kazuhiro SHIMIZU , Hajime AKIYAMA , Naoki YASUDA
发明人： Kazuhiro SHIMIZU , Hajime AKIYAMA , Naoki YASUDA
IPC分类号： H01L29/739 , H01L23/48 , H01L23/60 , H01L21/66
CPC分类号： H01L21/67271 , H01L21/67282 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.
摘要翻译：半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上。在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

8. 发明申请

US20120061639A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20120061639A1
公开(公告)日：2012-03-15
申请号：US13226974
申请日：2011-09-07
申请人： Naoki YASUDA
发明人： Naoki YASUDA
IPC分类号： H01L45/00
CPC分类号： H01L27/2463 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/72 , H01L27/2409
摘要： According to one embodiment, a resistance change memory includes a memory cell unit. The memory cell unit is configured to stack a resistance change element and a diode element having non-ohmic properties, and the diode element is configured to stack in order to a semiconductor layer having a first conductivity type, a semiconductor layer having a second conductivity type, and a semiconductor layer having the first conductivity type from the first interconnect layer side. An area density of dopant impurities in the semiconductor layer having the second conductivity type is larger than a sum total of area densities of dopant impurities in the two semiconductor layers having the first conductivity type, and smaller than double an area density of an electric flux number associated with a threshold electric field of an interband tunneling current of a material includes the semiconductor layer having the second conductivity type.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元单元。存储单元单元被配置为堆叠具有非欧姆特性的电阻变化元件和二极管元件，并且二极管元件被配置为堆叠以便具有第一导电类型的半导体层，具有第二导电类型的半导体层以及具有来自第一互连层侧的第一导电类型的半导体层。具有第二导电类型的半导体层中的掺杂剂杂质的面积密度大于具有第一导电类型的两个半导体层中的掺杂剂杂质的面积密度的总和，并且小于电通量的面积密度的两倍与材料的带间隧穿电流的阈值电场相关联，包括具有第二导电类型的半导体层。

9. 发明申请

US20120273869A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120273869A1
公开(公告)日：2012-11-01
申请号：US13545376
申请日：2012-07-10
申请人： Naoki YASUDA
发明人： Naoki YASUDA
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/283 , H01L21/76224 , H01L23/528 , H01L27/10805 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L28/40 , H01L28/60 , H01L29/0649 , H01L29/42324 , H01L29/4234 , H01L29/4925 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
摘要翻译：非易失性半导体存储器件包括在第一绝缘膜上的电荷存储层，设置在电荷存储层上的由层构成的第二绝缘膜和在第二绝缘膜上的控制栅电极。第二绝缘膜包括刚好位于电荷存储层上方的底层（A），设置在控制栅电极正下方的顶层（C）和设置在底层（A）和顶层（C）。中间层（B）具有比底层（A）和顶层（C）更高的势垒高度和更低的介电常数。中间层（B）的平均配位数小于顶层（C）的平均配位数和底层（A）的平均配位数。

10. 发明申请

US20110210387A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110210387A1
公开(公告)日：2011-09-01
申请号：US13103617
申请日：2011-05-09
申请人： Naoki YASUDA
发明人： Naoki YASUDA
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/283 , H01L21/76224 , H01L23/528 , H01L27/10805 , H01L27/115 , H01L27/11568 , H01L27/1157 , H01L28/40 , H01L28/60 , H01L29/0649 , H01L29/42324 , H01L29/4234 , H01L29/4925 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
摘要翻译：非易失性半导体存储器件包括在第一绝缘膜上的电荷存储层，设置在电荷存储层上的由层构成的第二绝缘膜和在第二绝缘膜上的控制栅电极。第二绝缘膜包括刚好位于电荷存储层上方的底层（A），设置在控制栅电极正下方的顶层（C）和设置在底层（A）和顶层（C）。中间层（B）具有比底层（A）和顶层（C）更高的势垒高度和更低的介电常数。中间层（B）的平均配位数小于顶层（C）的平均配位数和底层（A）的平均配位数。

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