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1. 发明授权

US5818380A Analog-digital converter capable of reducing a conversation error of an output signal 失效
标题翻译：模数转换器能够减少输出信号的转换误差
公开(公告)号：US5818380A
公开(公告)日：1998-10-06
申请号：US824549
申请日：1997-03-25
申请人： Masao Ito , Takahiro Miki , Shiro Hosotani
发明人： Masao Ito , Takahiro Miki , Shiro Hosotani
IPC分类号： H03M1/10 , H03K19/23 , H03M1/06 , H03M1/36
CPC分类号： H03M1/0602 , H03M1/361
摘要： A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.
摘要翻译：多数逻辑电路提供相邻三个比较器的输出值。多数逻辑电路作为输出信号输出所提供的三个输出值，包括至少两个相等的输出值。逆变器电路和AND电路产生并输出编码器的读取信号，该编码器是输出信号和输出信号的反相信号之间的逻辑积。

2. 发明授权

US5225837A A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US5225837A
公开(公告)日：1993-07-06
申请号：US706834
申请日：1991-05-29
申请人： Shiro Hosotani , Takahiro Miki , Masao Ito
发明人： Shiro Hosotani , Takahiro Miki , Masao Ito
IPC分类号： H03M1/36 , H03M1/78
CPC分类号： H03M1/362
摘要： An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage. The comparator includes capacitors for providing the difference between the input analogue signal and the reference voltage by a capacitor coupling, and an inverter amplifier for determining the positive or negative of the voltage change generated by the capacitors. This structure implements an A/D converter of high precision with less elements.
摘要翻译： A / D转换器包括产生参考电压的电阻网络，用于以来自电阻器网络的参考电压作为参考来检测输入模拟信号的电平的电平检测器，以及用于通过对输出进行编码来提供数字信号的编码器的电平检测器。电平检测器包括多个比较器，用于以来自电阻器网络的电阻器连接节点的预选电压作为参考电压对输入的模拟信号进行二维处理。电阻网络包括在接收第一参考电压的第一节点和接收第二参考电压的第二节点之间的多个电阻器元件，其互连以提供来自相关联的连接节点的电压，所述相关联的连接节点是所述第一参考电压和所述第二参考电压。比较器包括用于通过电容器耦合提供输入模拟信号和参考电压之间的差异的电容器，以及用于确定由电容器产生的电压变化的正或负的反相放大器。该结构实现了具有较低元件精度的A / D转换器。

3. 发明授权

US5315301A Binary data generating circuit and A/D converter having immunity to noise 失效
标题翻译：二进制数据产生电路和具有噪声抗扰度的A / D转换器
公开(公告)号：US5315301A
公开(公告)日：1994-05-24
申请号：US976056
申请日：1992-11-13
申请人： Shiro Hosotani , Takahiro Miki , Masao Ito
发明人： Shiro Hosotani , Takahiro Miki , Masao Ito
IPC分类号： H03M1/08 , H03M1/06 , H03M1/36
CPC分类号： H03M1/0643 , H03M1/068 , H03M1/361
摘要： An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.
摘要翻译：公开了一种改进的并行型A / D转换器，其包括由伪NMOS型ROM构成的编码器3和由伪PMOS型ROM构成的编码器28。这些编码器连接到预编码器2的输出。平均电路29接收从两个编码器提供的二进制数据，以将它们的平均值数据提供为转换的二进制输出数据。即使在多寻址的情况下，平均电路也可以提供作为转换数据的正确数据。结果，已经获得了不受噪声等影响的A / D转换器。

4. 发明授权

US5010338A Comparator circuit and analog to digital converter 失效
标题翻译：比较器电路和模数转换器
公开(公告)号：US5010338A
公开(公告)日：1991-04-23
申请号：US260126
申请日：1988-10-18
申请人： Takahiro Miki , Shiro Hosotani
发明人： Takahiro Miki , Shiro Hosotani
IPC分类号： H03K5/08 , H03K5/24 , H03M1/36
CPC分类号： H03K5/249 , H03M1/365
摘要： A comparator circuit capable of high-speed and accurate operation is disclosed. The comparator circuit includes an amplifier section 4, an inverter 5 connected to the output of the amplifier section 4, and a switching circuit 11 connected across the inverter 5. The amplifier section 4 contains a capacitor 1, an inverter 2 and a switching circuit 3 connected across the inverter 2. Coupled to the input of the amplifier section 4 are switching circuits 8 and 9 for supplying voltages V.sub.1 and V.sub.2 to be compared under timing control. During the first half cycle of comparing operation, the switching circuits 8, 3 and 11 are turned on while the switch circuit 9 is turned off. During the second half cycle of comparing operation, the switching circuit 9 is turned on while the switching circuits 8, 3 and 11 are turned off. The inverter 5, being short circuited by the switching circuit 11, produces a predetermined intermediate voltage during the first half of operating cycle, which is effective to generate voltage outputs accurately and exactly representing the compared results during the second half of the operating cycle.
摘要翻译：公开了一种能够高速且精确地操作的比较器电路。比较器电路包括放大器部分4，连接到放大器部分4的输出的反相器5和连接在反相器5两端的开关电路11.放大器部分4包含电容器1，反相器2和开关电路3 连接到逆变器2.耦合到放大器部分4的输入端，是用于提供电压V1和V2的开关电路8和9，以在定时控制下进行比较。在比较操作的前半周期期间，开关电路8,3和11在开关电路9断开时导通。在比较操作的第二个半周期期间，开关电路9导通，而开关电路8,3和11断开。由开关电路11短路的逆变器5在操作周期的前半部分期间产生预定的中间电压，这对于在操作周期的后半期期间精确地和准确地表示比较结果来产生电压输出是有效的。

5. 发明授权

US4900952A Voltage comparison apparatus 失效
标题翻译：电压比较装置
公开(公告)号：US4900952A
公开(公告)日：1990-02-13
申请号：US303778
申请日：1989-01-27
申请人： Shiro Hosotani , Takahiro Miki , Toshio Kumamoto
发明人： Shiro Hosotani , Takahiro Miki , Toshio Kumamoto
IPC分类号： G01R19/165 , H03K5/08 , H03K5/24
CPC分类号： H03K5/249
摘要： The voltage comparison apparatus of the invention features a timing control of clocks by which individual switches are ON/OFF controlled so that before a preceding amplifier circuit goes into comparison mode from auto zero mode, a successive amplifier circuit may go into auto zero mode from comparison mode, or before the preceding amplifier circuit goes into auto zero mode from comparison mode, the successive amplifier circuit may go into comparison mode from auto zero mode, whereby before the preceding amplifier circuit undergoes transition from the auto zero mode to the comparison mode, the successive amplifier circuit goes into the auto zero mode from the comparison mode, or before the preceding amplifier circuit undergoes transition from the comparison mode to the auto zero mode, the successive amplifier circuit goes into the comparison mode from the auto zero mode, and even when considerable variation occurs in input voltage difference during each clock cycle or clock time lags occurs, stable operation can be assured.
摘要翻译：本发明的电压比较装置具有对各个开关进行ON / OFF控制的时钟的定时控制，使得在前一放大器电路从自动归零模式进入比较模式之前，连续的放大器电路可以从比较进入自动零模式模式，或在比较模式之前的前一放大器电路进入自动归零模式之前，连续的放大器电路可以从自动调零模式进入比较模式，由此在之前的放大器电路经历从自动调零模式转换到比较模式之前，连续放大器电路从比较模式进入自动归零模式，或者在前一放大器电路从比较模式转换到自动归零模式之前，连续放大器电路从自动归零模式进入比较模式，甚至当在每个时钟周期或时钟时间滞后时，输入电压差异会发生相当大的变化遏制，稳定运行可以放心。

6. 发明授权

US5075688A Binary signal generating circuit with parallel sample and hold circuits and common sampling switch 失效
标题翻译：具有并行采样和保持电路的二进制信号发生电路和公共采样开关
公开(公告)号：US5075688A
公开(公告)日：1991-12-24
申请号：US622071
申请日：1990-12-04
申请人： Shiro Hosotani , Takahiro Miki
发明人： Shiro Hosotani , Takahiro Miki
IPC分类号： H03M1/36 , H03M1/06
CPC分类号： H03M1/0646 , H03M1/36
摘要： A single sampling switch i provided for a plurality of sample/hold function-equipped comparators. Thus, when the sampling switch is turned on, an analog signal is fed to each sample and hold circuit, and when it is turned off, the analog signal fed in at that time is sampled and held in each sample/hold function-equipped comparator. The analog signal values sampled and held in the sample/hold function-equipped comparators are averaged when the averaging switch is turned on. In this manner, since the timing for sampling and holding is controlled by the single sampling switch, a smaller number of switching elements are sufficient and the possibility of the timing for sampling and holding differing between the sample/hold function-equipped comparators is eliminated.
摘要翻译：单个采样开关i设置用于多个采样/保持功能的比较器。因此，当采样开关接通时，模拟信号被馈送到每个采样和保持电路，并且当其被截止时，馈入的模拟信号在该时间被采样并保持在每个采样保持功能的比较器。采样保持在采样/保持功能的比较器中的模拟信号值在平均开关导通时被平均。以这种方式，由于采样和保持的定时由单采样开关控制，所以较少数量的开关元件是足够的，并且消除了具有采样/保持功能的比较器之间的取样和保持定时不同的可能性。

7. 发明授权

US4912470A Ad converter 失效
标题翻译：广告转换器
公开(公告)号：US4912470A
公开(公告)日：1990-03-27
申请号：US260130
申请日：1988-10-18
申请人： Shiro Hosotani , Takahiro Miki
发明人： Shiro Hosotani , Takahiro Miki
IPC分类号： H03M1/14 , H03M1/06
CPC分类号： H03M1/0602 , H03M1/147
摘要： A serial-parallel type AD converter comprises a first parallel type AD converting portion determining a higher order bit of a digital signal, a second parallel type AD converting portion determining a lower order bit of the digital signal and error correcting circuit. In the first parallel type Ad converting portion, a shifter is connected between a first determining circuit and a first encoder. In the second parallel type AD converting portion, a selector is connected between three second voltage comparator groups and a second determining circuit. The error correcting circuit applies control signals to the shifter and the selector for correcting errors derived from sampling skew of analog input voltages. The shifter determines the connection between the first determining circuit and first encoder in response to the control signal. The selector connects one of the three voltage comparator groups to the second determining circuit in response to the control signal.
摘要翻译：串行并行型AD转换器包括确定数字信号的较高阶位的第一并行型AD转换部分，确定数字信号的低位位的第二并行型AD转换部分和纠错电路。在第一并行型Ad转换部分中，移位器连接在第一确定电路和第一编码器之间。在第二并联型AD转换部分中，选择器连接在三个第二电压比较器组和第二确定电路之间。误差校正电路向移位器和选择器施加控制信号，用于校正由模拟输入电压的采样偏差导出的误差。移位器响应于控制信号确定第一确定电路和第一编码器之间的连接。选择器响应于控制信号将三个电压比较器组中的一个连接到第二确定电路。

8. 发明授权

US5327135A Series-parallel A-D converter 失效
标题翻译：串并联A-D转换器
公开(公告)号：US5327135A
公开(公告)日：1994-07-05
申请号：US12406
申请日：1993-02-02
申请人： Shiro Hosotani , Takahiro Miki
发明人： Shiro Hosotani , Takahiro Miki
IPC分类号： H03M1/14 , H03M1/36
CPC分类号： H03M1/148 , H03M1/365
摘要： Low-order reference potentials including high-order reference potentials (VRT, VRB, VC0 to VC6) generated from a ladder resistor and potentials (V(i, j) (i=0 to 7, j=0 to 6)) are applied to potential lines, respectively, to be transmitted by various switches to analog bus lines (FR0a to FR14a) or analog bus lines (FR0b FR14b). The low-order reference potentials are applied to the analog bus lines (FR0b to FR14b) when it is judged that a sample signal potential falls in voltage zones (Z0 to Z3) as a result of comparison with the high-order reference potentials and are applied to the analog bus lines (FR0a to FR14a) when it is judged that the sample signal potential falls in voltage zones (Z4 to Z7). This provides for reduction in the number of switches connected to each analog bus line and in parasitic capacitance, so that a settling time of the low-order reference potentials is shortened. High-speed operation of a series-parallel A-D converter is achieved.
摘要翻译：应用梯形电阻产生的高阶参考电位（VRT，VRB，VC0〜VC6）和电位（V（i，j）（i = 0〜7，j = 0〜6））的低阶参考电位分别由各种开关传输到模拟总线（FR0a至FR14a）或模拟总线（FR0b FR14b）的电位线。作为与高阶参考电位进行比较的结果，当判断为采样信号电位落在电压区（Z0〜Z3））时，将低阶参考电位施加到模拟总线（FR0b〜FR14b），分别为当判断为采样信号电位落在电压区域（Z4〜Z7）时，施加到模拟总线（FR0a〜FR14a）。这提供了减少连接到每个模拟总线线路和寄生电容的开关的数量，使得低阶参考电位的建立时间缩短。实现串并联A-D转换器的高速运行。

9. 发明授权

US5160930A Reference voltage generating circuit, and A/D and D/A converters using the same 失效
标题翻译：参考电压发生电路，以及使用其的A / D和D / A转换器
公开(公告)号：US5160930A
公开(公告)日：1992-11-03
申请号：US665856
申请日：1991-03-07
申请人： Shiro Hosotani , Takahiro Miki
发明人： Shiro Hosotani , Takahiro Miki
IPC分类号： H03M1/36 , H03M1/74
CPC分类号： H03M1/362
摘要： A reference voltage generating circuit is disclosed which generates a plurality of linear analog voltages and is desirably applied to A/D and D/A converters. As the reference voltage generating circuit itself or a resistor network comprised therein, a resistor network is employed which comprises a plurality of resistor elements connected in series between two power sources and resistor networks (or resistor elements) connected to all the other nodes than the two nodes closest to the two power sources, respectively, out of the nodes between the former resistor elements. The above-mentioned plurality of resistor elements have the same resistance value r and the output impedance (or resistance value) of the resistor networks (or resistor elements) connected to all the nodes above is set to a value twice the resistance value r of the above-mentioned resistor elements, or 2r. Accordingly, output impedance at any of the nodes between said plurality of resistor elements represents 2.multidot.r/3. A a result, inequality of output impedances between the output terminals of the reference voltage generating circuit can be improved.
摘要翻译：公开了一种产生多个线性模拟电压的参考电压产生电路，并期望地应用于A / D和D / A转换器。作为参考电压产生电路本身或其中包含的电阻网络，采用电阻网络，其包括串联连接在两个电源和电阻器网络（或电阻器元件）之间的多个电阻元件，所述电阻器网络连接到除了两个最靠近两个电源的节点分别位于前一个电阻元件之间的节点之间。上述多个电阻元件具有相同的电阻值r，并且连接到上述所有节点的电阻器网络（或电阻元件）的输出阻抗（或电阻值）被设置为两倍于上述电阻元件，或2r。因此，所述多个电阻元件之间的任何节点处的输出阻抗表示2×r / 3。结果，可以提高参考电压产生电路的输出端子之间的输出阻抗的不等式。

10. 发明授权

US4958157A Encoder circuit with series connected output switching transistors 失效
标题翻译：编码器电路与串联连接的输出开关晶体管
公开(公告)号：US4958157A
公开(公告)日：1990-09-18
申请号：US310112
申请日：1989-02-14
申请人： Takahiro Miki , Shiro Hosotani
发明人： Takahiro Miki , Shiro Hosotani
IPC分类号： H03M7/00 , H03M1/36 , H03M7/08 , H03M7/20
CPC分类号： H03M7/20
摘要： An encoder circuit is disclosed wherein a plurality of input signals are parallel-supplied directly to the gates of transistor pairs. Each transistor pair comprises at least two series-connected transistors which are provided between an associated one of output lines and a source of a predetermined potential level (a supply potential or groud potential). The encoding function of the circuit is performed by turning on and off the transistors.
摘要翻译：公开了一种编码器电路，其中多个输入信号被并行地提供给晶体管对的栅极。每个晶体管对包括至少两个串联连接的晶体管，其被提供在相关联的一个输出线和预定电位电平（电源电位或电位）之间。通过接通和关断晶体管来执行电路的编码功能。

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