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1. 发明授权

US5185517A Semiconductor integrated circuit for measuring distance for automatic focusing 失效
标题翻译：半导体集成电路，用于测量自动对焦的距离
公开(公告)号：US5185517A
公开(公告)日：1993-02-09
申请号：US831441
申请日：1992-02-05
申请人： Masanori Inamori , Toshihide Miyake
发明人： Masanori Inamori , Toshihide Miyake
IPC分类号： G01S7/497 , G01S17/46
CPC分类号： G01S7/497 , G01S17/46
摘要： For use with an automatic focusing device, a semiconductor integrated circuit is provided for measuring distance having a light-detecting element for receiving light from an object, the distance to the subject is to be measured, and outputting a signal according to the distance from the object. The semiconductor integrated circuit is formed in one chip and includes a distance measurement arithmetic unit for forming digital distance measurement data inversely proportional to the distance to the object from the signal from the light-detecting element; a memory unit for writing therein two items of distance measurement data output from the distance measurement arithmetic unit with regard to two known distances in a calibration mode, and a data arithmeteic unit for computing an automatic focusing device control signal from the two items of distances measurement data stored in the memory unit and distance measurement data output from the distance measurement arithmetic unit in a distance measuring mode.
摘要翻译：为了与自动聚焦装置一起使用，提供半导体集成电路用于测量具有用于接收来自物体的光的光检测元件的距离，要测量到被摄体的距离，并且根据距离物体的距离输出信号目的。半导体集成电路形成在一个芯片中，并且包括距离测量运算单元，用于根据来自光检测元件的信号形成与物体的距离成反比的数字距离测量数据; 存储单元，用于在校准模式中写入距距离测量运算单元输出的两个距离测量数据相对于两个已知距离;以及数据算术单元，用于计算来自两个距离测量的自动聚焦设备控制信号存储在存储单元中的数据和距离测量运算单元在距离测量模式下输出的距离测量数据。

2. 发明授权

US5304873A Log compressing circuit providing capability of keeping clamp level independent of variety of amplification factor 失效
标题翻译：记录压缩电路提供保持钳位电平独立于各种放大因子的能力
公开(公告)号：US5304873A
公开(公告)日：1994-04-19
申请号：US994789
申请日：1992-12-22
申请人： Masanori Inamori , Toshihide Miyake
发明人： Masanori Inamori , Toshihide Miyake
IPC分类号： H03G11/02 , H03G7/00 , H03G11/04 , G06G7/24 , H03D1/00
CPC分类号： H03G7/001
摘要： A log compressing circuit is arranged so that the clamping level is independent of the amplification factor of a first transistor for amplifying input current. The log compressing circuit includes the first transistor for amplifying input current, a compressing diode for log-compressing the amplified current, a clamp voltage generating diode serving as a source for generating a clamping voltage, and a second transistor for clamping the log-compressed voltage if the voltage goes beyond a predetermined clamp voltage. The second transistor has the same form as the first transistor and provides a collector connected to a cathode of the clamp voltage generating diode. The constant current is supplied to the second transistor from a constant current source.
摘要翻译：对数压缩电路被布置成使得钳位电平与用于放大输入电流的第一晶体管的放大系数无关。对数压缩电路包括用于放大输入电流的第一晶体管，用于对放大电流进行对数压缩的压缩二极管，用作产生钳位电压的源的钳位电压产生二极管和用于钳位对数压缩电压的第二晶体管如果电压超过预定的钳位电压。第二晶体管具有与第一晶体管相同的形式，并提供连接到钳位电压产生二极管的阴极的集电极。恒定电流从恒定电流源提供给第二晶体管。

3. 发明授权

US5381083A Constant-current power-supply circuit formed on an IC 失效
标题翻译：在IC上形成恒流电源电路
公开(公告)号：US5381083A
公开(公告)日：1995-01-10
申请号：US76971
申请日：1993-06-16
申请人： Masanori Inamori , Toshihide Miyake
发明人： Masanori Inamori , Toshihide Miyake
IPC分类号： G05F3/22 , G05F3/26 , G05F3/16
CPC分类号： G05F3/265 , G05F3/222
摘要： There are provided a first constant-current circuit and a second constant-current circuit, and a first resistor connected in series with the first constant-current circuit generates a band-gap voltage. The first constant-current circuit and the second constant-current circuit constitute a current Miller circuit, and a part of a current that flows through the second resistor connected in series with the second constant-current circuit is outputted as a constant current source. The constant-current power supply IC, which has the above-mentioned arrangement, is designed as follows: the first resistor and the second resistor have a predetermined line-width ratio that is determined in such a manner that if the respective line-widths vary by virtually the same value, a varied amount in the second constant current value that has been caused by a variation in the value of resistivity of the first resistor is cancelled by a varied amount caused by a variation in the value of resistivity of the second resistor. This arrangement is effective in compensating function and makes it possible to minimize the error on the constant current output due to deviations that occur during production.
摘要翻译：提供第一恒流电路和第二恒流电路，并且与第一恒流电路串联连接的第一电阻器产生带隙电压。第一恒流电路和第二恒流电路构成电流米勒电路，并且流过与第二恒流电路串联连接的第二电阻器的一部分电流作为恒流源输出。具有上述结构的恒流电源IC设计如下：第一电阻器和第二电阻器具有预定的线宽比，其以如下方式确定：如果各个线宽变化通过实质上相同的值，由第一电阻器的电阻率值的变化引起的第二恒定电流值的变化量被由第二电阻器的电阻率值的变化引起的变化量抵消。这种布置在补偿功能方面是有效的，并且可以使由于在生产期间发生的偏差导致的恒定电流输出的误差最小化。

4. 发明授权

US06720761B1 Hall device biasing circuit and magnetism detection circuit including the same 有权
标题翻译：霍尔器件偏置电路和磁检测电路包括它们
公开(公告)号：US06720761B1
公开(公告)日：2004-04-13
申请号：US09696006
申请日：2000-10-26
申请人： Hiroki Doi , Masanori Inamori
发明人： Hiroki Doi , Masanori Inamori
IPC分类号： G01B714
CPC分类号： G01R33/07
摘要： A Hall device biasing circuit includes a plurality of terminals for applying a bias voltage to a plurality of Hall devices connected in series, respectively. A magnetism detection circuit includes a plurality of Hall devices connected in series; and a Hall device biasing circuit including at least a plurality of terminals corresponding to the plurality of Hall devices for supplying a constant bias voltage to each of the plurality of Hall devices respectively from the plurality of terminals.
摘要翻译：霍尔器件偏置电路包括分别对串联连接的多个霍尔器件施加偏置电压的多个端子。磁检测电路包括串联连接的多个霍尔器件; 以及霍尔器件偏置电路，其至少包括对应于多个霍尔器件的多个端子，用于分别从多个端子向多个霍尔器件中的每一个提供恒定的偏置电压。

5. 发明授权

US07166916B2 Manufacturing method for semiconductor integrated circuit, semiconductor integrated circuit, and semiconductor integrated circuit apparatus 有权
标题翻译：半导体集成电路的制造方法，半导体集成电路和半导体集成电路装置
公开(公告)号：US07166916B2
公开(公告)日：2007-01-23
申请号：US10996857
申请日：2004-11-23
申请人： Tetsuya Akamatsu , Masanori Inamori
发明人： Tetsuya Akamatsu , Masanori Inamori
IPC分类号： H01L23/34
CPC分类号： H01L24/12 , H01L21/561 , H01L23/3114 , H01L23/3128 , H01L23/525 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0231 , H01L2224/0401 , H01L2224/13099 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor integrated circuit is so structured that a first insulating layer is formed on a surface of a semiconductor chip and a second insulating layer covers an entire region of the surface of the semiconductor chip. Via apertures made to the second insulating layer, an electrical connection configuration is formed from above the second insulating layer by using gold wires. Then, an electronic component is mounted on the second insulating layer. By arranging as such, the electronic component is mounted on the semiconductor chip in advance. Therefore, it is possible to further reduce mounting space on a printed-wiring board and also possible to make is easy to attain one-packaged IC.
摘要翻译：半导体集成电路的结构使得在半导体芯片的表面上形成第一绝缘层，并且第二绝缘层覆盖半导体芯片的表面的整个区域。通过制造到第二绝缘层的孔，通过使用金线从第二绝缘层的上方形成电连接构造。然后，将电子部件安装在第二绝缘层上。通过这样安排，电子部件预先安装在半导体芯片上。因此，可以进一步减少印刷电路板上的安装空间，并且也可以容易地实现单封装IC。

6. 发明授权

US06803807B2 Negative voltage output charge pump circuit 失效
标题翻译：负电压输出电荷泵电路
公开(公告)号：US06803807B2
公开(公告)日：2004-10-12
申请号：US10358189
申请日：2003-02-05
申请人： Toshiya Fujiyama , Masanori Inamori , Hiroki Doi
发明人： Toshiya Fujiyama , Masanori Inamori , Hiroki Doi
IPC分类号： G05F110
CPC分类号： H02M3/07 , H02M2003/071
摘要： In a negative voltage output charge pump circuit, first a capacitor C1 is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C1 is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C1 is made to conduct to an output terminal OUT so that the voltage with which the capacitor C1 is charged is output as a negative voltage −Vin. Here, at least one of the switching device DP1 that is kept on while the capacitor C1 is being charged so as to apply the reference voltage to the point B and the switching device DP2 that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.
摘要翻译：在负电压输出电荷泵电路中，首先，电容器C1相对于参考电压被充有正电压Vin，然后使电容器C1的高电位端子A导通到参考电压，同时低电平使电容器C1的电位端子B导通到输出端子OUT，使得电容器C1被充电的电压被输出为负电压-Vin。这里，开关装置DP1中的至少一个在电容器C1正在被充电的同时保持接通，以便在输出负电压的同时将参考电压施加到点B和保持开关的开关装置DP2，从而使点B导通到输出端子OUT是耗尽型晶体管。通过这样的结构，能够实现低损耗运转的寄生装置不产生故障的负电压输出电荷泵电路，能够以低成本生产。

7. 发明授权

US06473316B2 Phase control circuit and switching regulator 有权
公开(公告)号：US06473316B2
公开(公告)日：2002-10-29
申请号：US09963611
申请日：2001-09-27
申请人： Toshiya Fujiyama , Masanori Inamori
发明人： Toshiya Fujiyama , Masanori Inamori
IPC分类号： H02M3315
CPC分类号： H02M7/53871 , Y02B70/1441
摘要： A phase control circuit which can stabilize voltage control when used in a switching regulator, and a switching regulator using such a phase control circuit are provided. A switching circuit for generating a first and a second output signals having opposite polarities based on a clock signal, is provided. A PWM latch circuit, reset by a reset signal, for generating a third and a fourth output signals which have phases controlled with respect to the first and the second output signals respectively by a set signal produced based on a control signal and come to have opposite polarities, is provided. A delay circuit for delaying the rising of each of the first through the fourth output signals before outputting each of the first through the fourth output signals is provided for each output signal. A delay clock pulse width setting circuit for generating a delay pulse based on low level periods of the delayed first and second output signals is provided so as to reset the PWM latch circuit using the delay pulse as the reset signal.

8. 发明授权

US06400201B1 Delay circuit and ring oscillator incorporating the same 失效
标题翻译：延迟电路和包含其的环形振荡器
公开(公告)号：US06400201B1
公开(公告)日：2002-06-04
申请号：US09945654
申请日：2001-09-05
申请人： Masanori Inamori , Syouji Sakurai , Toshiya Fujiyama , Hiroki Doi
发明人： Masanori Inamori , Syouji Sakurai , Toshiya Fujiyama , Hiroki Doi
IPC分类号： H03H1126
CPC分类号： H03K5/13 , H03K3/0315 , H03K2005/00058
摘要： A delay circuit in accordance with the present invention includes: a first I2L inverter and a second I2L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters, wherein: the delay circuit further includes a current adjusting circuit having at least one third I2L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I2L inverter; and the current adjusting circuit is connected to adjust a charge current of the capacitor. The configuration provides a delay circuit of simple circuit structure that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also provides a ring oscillator incorporating the delay circuit.
摘要翻译：根据本发明的延迟电路包括：彼此串联连接的第一I2L反相器和第二I2L反相器; 以及插入在所述第一和第二反相器的接地点和连接点之间的电容器，其中：所述延迟电路还包括电流调节电路，所述电流调节电路具有至少一个第三I2L反相器，其具有多个输出端子，所述多个输出端子中的至少一个连接到第三I2L逆变器的输入端; 并且电流调节电路被连接以调节电容器的充电电流。该配置提供了简单的电路结构的延迟电路，其占据集成电路中的小面积并且能够引入任何给定的延迟，并且还提供并入延迟电路的环形振荡器。

9. 发明授权

US06392444B1 IIL reset circuit 失效
标题翻译： IIL复位电路
公开(公告)号：US06392444B1
公开(公告)日：2002-05-21
申请号：US09546660
申请日：2000-04-10
申请人： Masanori Inamori , Hiroki Doi
发明人： Masanori Inamori , Hiroki Doi
IPC分类号： H03L700
CPC分类号： H03K17/22
摘要： An IIL reset circuit includes an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal. When the IIL inverter is supplied with a constant current, it charges the capacitor through the input terminal, and outputs a reset pulse through the output terminal. The reset pulse has a pulse width that is determined based on both a current supplied to the capacitor, and on a capacitance of the capacitor.
摘要翻译： IIL复位电路包括具有输入和输出端子的IIL反相器，以及通过输入端子连接到IIL反相器的电容器。当IIL逆变器提供恒流时，通过输入端对电容充电，并通过输出端输出复位脉冲。复位脉冲具有基于提供给电容器的电流和电容器的电容确定的脉冲宽度。

10. 发明授权

US5767741A Self compensating differential circuit 失效
标题翻译：自补偿差分电路
公开(公告)号：US5767741A
公开(公告)日：1998-06-16
申请号：US662138
申请日：1996-06-12
申请人： Masanori Inamori
发明人： Masanori Inamori
IPC分类号： H03G7/06 , H03F1/08 , H03F3/45 , H03G1/00 , H03G11/08
CPC分类号： H03G1/0023 , H03F3/45085 , H03F3/45098 , H03F2203/45141 , H03F2203/45562 , H03F2203/45571 , H03F2203/45594 , H03F2203/45612 , H03F2203/45644 , H03F2203/45652 , H03F2203/45658 , H03F2203/45696 , H03F2203/45702
摘要： The invention presents a differential circuit capable of compensating for an error in differential output caused by voltage drop due to the emitter series resistance of transistors without being affected by the values of differential input currents and the current ratio of the input currents. A differential circuit comprises NPN type first and second transistors QA, QB, first and second resistors RA, RB connected between the collectors of the first and second transistors and a DC source voltage, means for connecting the collector of the first transistor to the base of the second transistor, means for connecting the collector of the second transistor to the base of the first transistor, first and second differential current input terminals TA,TB connected to the emitters of the first and second transistors, NPN type third and fourth transistors having their bases connected to the emitters of the first and second transistors, and emitters commonly connected to a constant current source IO, and first and second output terminals T1, T2 connected respectively to the collectors of the third and fourth transistors.
摘要翻译：本发明提出了一种差分电路，其能够补偿由于晶体管的发射极串联电阻引起的电压降引起的差分输出误差，而不受差分输入电流的值和输入电流的电流比的影响。差分电路包括NPN型第一和第二晶体管QA，QB，连接在第一和第二晶体管的集电极之间的第一和第二电阻器RA，RB和DC源极电压，用于将第一晶体管的集电极连接到第一晶体管的基极的装置第二晶体管，用于将第二晶体管的集电极连接到第一晶体管的基极的装置，连接到第一和第二晶体管的发射极的第一和第二差分电流输入端子TA，TB，NPN型第三和第四晶体管，连接到第一和第二晶体管的发射极的基极以及共同连接到恒流源IO的发射极以及分别连接到第三和第四晶体管的集电极的第一和第二输出端子T1，T2。

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