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1. 发明授权

US07587574B2 Address translation information storing apparatus and address translation information storing method 失效
标题翻译：地址转译信息存储装置和地址转换信息存储方法
公开(公告)号：US07587574B2
公开(公告)日：2009-09-08
申请号：US10986136
申请日：2004-11-12
申请人： Masanori Doi , Iwao Yamazaki , Tsuyoshi Motokurumada , Masahiro Doteguchi
发明人： Masanori Doi , Iwao Yamazaki , Tsuyoshi Motokurumada , Masahiro Doteguchi
IPC分类号： G06F12/10
CPC分类号： G06F12/1018 , G06F12/1027 , G06F12/1036
摘要： Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.
摘要翻译：获取与虚拟地址有关的上下文信息，并且基于上下文信息来确定用于存储地址转换信息的存储位置。

2. 发明申请

US20060026381A1 Address translation information storing apparatus and address translation information storing method 失效
公开(公告)号：US20060026381A1
公开(公告)日：2006-02-02
申请号：US10986136
申请日：2004-11-12
申请人： Masanori Doi , Iwao Yamazaki , Tsuyoshi Motokurumada , Masahiro Doteguchi
发明人： Masanori Doi , Iwao Yamazaki , Tsuyoshi Motokurumada , Masahiro Doteguchi
IPC分类号： G06F12/10
CPC分类号： G06F12/1018 , G06F12/1027 , G06F12/1036
摘要： Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.

3. 发明授权

US07617379B2 Multi-hit control method for shared TLB in a multiprocessor system 失效
标题翻译：多处理器系统中共享TLB的多命中控制方法
公开(公告)号：US07617379B2
公开(公告)日：2009-11-10
申请号：US10986891
申请日：2004-11-15
申请人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
发明人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/1045
摘要： The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.
摘要翻译：本发明包括：用于在多个线程之间共享地址转换缓冲器（TLB = Translation Lookaside Buffer），而不在多线程模式下操作的信息处理器中产生不期望的多命中;地址转换缓冲器，用于存储地址转换对，线程信息，用于从地址转换缓冲器检索与所述虚拟地址相同的虚拟地址的地址转换对用于将虚拟地址转换为物理地址的检索器;确定单元，用于当多个地址转换对由检索者，对应于多个地址转换对的多个线程信息中的两个或更多个所述线程信息是否相同;以及多命中控制器，用于抑制多命中的输出并且如果线程信息被确定则指示执行地址转换根据不同而不同授权单位

4. 发明申请

US20060026382A1 Information processor and multi-hit control method 失效
标题翻译：信息处理器和多命中控制方法
公开(公告)号：US20060026382A1
公开(公告)日：2006-02-02
申请号：US10986891
申请日：2004-11-15
申请人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
发明人： Takahito Hirano , Iwao Yamazaki , Tsuyoshi Motokurumada
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/1045
摘要： The present invention comprises, for enabling sharing an address translation buffer (TLB=Translation Lookaside Buffer) between plural threads without generating undesirable multi-hits in an information processor which operates in multi-thread mode, an address translation buffer for storing address translation pairs and thread information, a retriever for retrieving an address translation pair of a virtual addresses identical to said virtual address from the address translation buffer for translating the virtual address into a physical address, a determination unit for determining, when plural addresses translation pairs are retrieved by the retriever, whether or not two or more of said thread information are identical among plural thread information corresponding to plural address translation pairs, and a multi-hit controller for suppressing output of multi-hits and directing execution of address translation if the thread information are determined to be different according to the determination unit.
摘要翻译：本发明包括：用于在多个线程之间共享地址转换缓冲器（TLB = Translation Lookaside Buffer），而不在多线程模式下操作的信息处理器中产生不期望的多命中;地址转换缓冲器，用于存储地址转换对，线程信息，用于从地址转换缓冲器检索与所述虚拟地址相同的虚拟地址的地址转换对用于将虚拟地址转换为物理地址的检索器;确定单元，用于当多个地址转换对由检索者，对应于多个地址转换对的多个线程信息中的两个或更多个所述线程信息是否相同;以及多命中控制器，用于抑制多命中的输出并且如果线程信息被确定则指示执行地址转换根据不同而不同授权单位

5. 发明授权

US06915406B2 Address translation apparatus, address translation method, and two-layer address translation apparatus 有权
标题翻译：地址转换装置，地址转换方法和双层地址转换装置
公开(公告)号：US06915406B2
公开(公告)日：2005-07-05
申请号：US10330322
申请日：2002-12-30
申请人： Takuma Chiba , Tsuyoshi Motokurumada , Iwao Yamazaki
发明人： Takuma Chiba , Tsuyoshi Motokurumada , Iwao Yamazaki
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A first table stores operand data for translation of operand virtual address into a physical address. A second table stores instruction data for translation of instruction virtual address into a physical address. The first and the second tables are formed in one memory. If operand access and instruction access are generated simultaneously, the operand access is executed with priority and the instruction virtual address is held in a wait register after that the instruction access is executed after finishing the operand access based on a wait instruction virtual address.
摘要翻译：第一表存储用于将操作数虚拟地址转换为物理地址的操作数数据。第二表存储用于将指令虚拟地址转换成物理地址的指令数据。第一和第二表形成在一个存储器中。如果同时产生操作数访问和指令访问，则优先执行操作数访问，并且在根据等待指令虚拟地址完成操作数访问之后执行指令访问之后，将指令虚拟地址保存在等待寄存器中。

6. 发明授权

US07380097B2 Apparatus and method for controlling address conversion buffer 有权
标题翻译：用于控制地址转换缓冲器的装置和方法
公开(公告)号：US07380097B2
公开(公告)日：2008-05-27
申请号：US10986041
申请日：2004-11-12
申请人： Masanori Doi , Iwao Yamazaki
发明人： Masanori Doi , Iwao Yamazaki
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.
摘要翻译：一种用于控制地址转换缓冲器的方法，该处理器能够在一个核心上同时执行多个线程的处理器上，包括在地址转换缓冲器的条目中注册地址转换信息，该条目包括由一个线程可用的第一存储区域以及在所有线程之间共享的第二存储器区域，将所述第二存储器区域的一部分分配为所述第一存储区域的交换区域，并且基于由所述处理器执行的线程切换将所述交换区域中的数据传送到所述第一存储器区域。

7. 发明申请

US20060026380A1 Apparatus and method for controlling address conversion buffer 有权
标题翻译：用于控制地址转换缓冲器的装置和方法
公开(公告)号：US20060026380A1
公开(公告)日：2006-02-02
申请号：US10986041
申请日：2004-11-12
申请人： Masanori Doi , Iwao Yamazaki
发明人： Masanori Doi , Iwao Yamazaki
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.
摘要翻译：一种用于控制地址转换缓冲器的方法，该处理器能够在一个核心上同时执行多个线程的处理器上，包括在地址转换缓冲器的条目中注册地址转换信息，该条目包括可由一个线程使用的第一存储区域以及在所有线程之间共享的第二存储器区域，将所述第二存储器区域的一部分分配为所述第一存储区域的交换区域，并且基于由所述处理器执行的线程切换将所述交换区域中的数据传送到所述第一存储区域。

8. 发明申请

US20120296322A1 LASER TREATMENT DEVICE 审中-公开
标题翻译：激光治疗装置
公开(公告)号：US20120296322A1
公开(公告)日：2012-11-22
申请号：US13521962
申请日：2011-03-10
申请人： Iwao Yamazaki , Akitsugu Yamazaki
发明人： Iwao Yamazaki , Akitsugu Yamazaki
IPC分类号： A61B18/20
CPC分类号： A61B18/203 , A61B2017/00057 , A61B2018/00452 , A61B2018/00636 , A61B2018/00702 , A61B2018/00785 , A61B2018/208
摘要： [Problem to be Solved] It cannot be said that the irradiation range of laser light is sufficiently wide, a lot of labor is taken to irradiate the skin with laser light, and there has been a problem that efficiency of cosmetic treatment is bad.[Solution] A laser treatment device is provided with a laser light source 40 consisting of at least one or more VCSEL array 41 that has two or more VCSEL elements 41s arranged on a single wafer and emits laser light for irradiating the skin. The laser treatment device may also be provided with: a reflected-light power detection means that detects power of reflected light of the light irradiating an irradiation part, the reflected light reflected from the irradiation part; and a control means that adjusts, in accordance with the power of the reflected light detected by the reflected-light power detection means, power of the laser light emitted from the light source means.
摘要翻译： [待解决的问题]不能说激光的照射范围足够宽，用激光照射皮肤大量劳动，并且存在化妆品处理效率差的问题。 [解决方案]激光治疗装置设置有由至少一个或多个VCSEL阵列41组成的激光源40，所述VCSEL阵列41具有布置在单个晶片上的两个或更多个VCSEL元件41s，并且发射用于照射皮肤的激光。激光治疗装置还可以设置有：反射光功率检测装置，其检测照射部分的光的反射光的功率，从照射部反射的反射光; 以及控制装置，其根据由反射光功率检测装置检测的反射光的功率调整从光源装置发射的激光的功率。

9. 发明申请

US20110161593A1 Cache unit, arithmetic processing unit, and information processing unit 有权
标题翻译：高速缓存单元，算术处理单元和信息处理单元
公开(公告)号：US20110161593A1
公开(公告)日：2011-06-30
申请号：US12929026
申请日：2010-12-22
申请人： Iwao Yamazaki
发明人： Iwao Yamazaki
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F2212/1028 , Y02D10/13
摘要： A cache unit comprising a register file that selects an entry indicated by a cache index of n bits (n is a natural number) that is used to search for an instruction cache tag, using multiplexer groups having n stages respectively corresponding to the n bits of the cache index. Among the multiplexer groups having n stages, a multiplexer group in an mth stage has 2(m-1) multiplex circuits. The multiplexer group in the mth stage uses a value of an mth bit (m is a natural number equal to or less than n) from the least significant bit in the cache index as a control signal. The multiplexer group in the mth stage switches all multiplex circuits included in the multiplexer group in the mth stage in accordance with the control signal.
摘要翻译：一种高速缓存单元，包括一个寄存器文件，该寄存器文件选择由用于搜索指令高速缓存标签的n位（n是自然数）的高速缓存索引指示的条目，使用具有分别对应于n个缓存索引。在具有n级的多路复用器组中，第m级的复用器组具有2（m-1）个复用电路。第m级中的多路复用器组作为控制信号使用来自高速缓存索引中的最低有效位的第m位（m为等于或小于n的自然数）的值。第m级的复用器组根据控制信号切换第m级中的复用器组中包括的所有多路复用电路。

10. 发明申请

US20070173906A1 Electrode for treatment and device for treatment 审中-公开
标题翻译：用于治疗的电极和治疗装置
公开(公告)号：US20070173906A1
公开(公告)日：2007-07-26
申请号：US10587865
申请日：2005-01-28
申请人： Iwao Yamazaki
发明人： Iwao Yamazaki
IPC分类号： A61N1/36
CPC分类号： A61N1/0452 , A61N1/0484 , A61N1/0492 , A61N1/08 , A61N1/32
摘要： A metal backer forming device (1), comprising a film withdrawing roller (2) for withdrawing, starting at one end, a transfer film (F) from the wound body of the transfer film (F) formed by applying at least a metal film (26a) onto a base film (26b), a film carrying mechanism such as a turn roller (9) for carrying the transfer film (F) withdrawn from the wound body to the downstream side, a transfer roller (12) for transferring the metal film (26a) by heating while pressing the carried transfer film (F) against a phosphor screen (22) installed on a face plate (27), and a film winding roller (18) for winding while releasing the base film (26b) from the transfer film (F) which completes transfer treatment.
摘要翻译：一种金属支撑件形成装置（1），包括一个退色辊（2），用于从一端开始从转印膜（F）的卷绕体开始转印膜（F），所述转印膜（F）至少通过涂覆金属膜（26a）到基膜（26b）上，用于承载从卷绕体退出到下游侧的转印膜（F）的转膜辊（9）的膜承载机构，用于在将所携带的转印膜（F）压靠在安装在面板（27）上的荧光屏（22）上的同时通过加热转印金属膜（26a）;以及胶片卷绕辊（18），用于在释放基膜（26b）从转印膜（F）完成转印处理。

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