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1. 发明授权

US5747844A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
公开(公告)号：US5747844A
公开(公告)日：1998-05-05
申请号：US736279
申请日：1996-10-24
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

2. 发明授权

US5578847A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
标题翻译：具有更高密度位线/字线布局的动态半导体存储器件
公开(公告)号：US5578847A
公开(公告)日：1996-11-26
申请号：US402570
申请日：1995-03-13
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
摘要翻译：设置在一个位线BL上的多个位线触点布置在每个设置在每个相邻的两个字线WL之间的每隔一个空间中，并且设置在相邻位线BL上的多个位线触点彼此布置每个相邻的两个字线WL之间的空间不同于其中布置在前位线上形成的位线触点中的相应一个的空间。

3. 发明授权

US5488242A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5488242A
公开(公告)日：1996-01-30
申请号：US156931
申请日：1993-11-24
申请人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
发明人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10829
摘要： In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.
摘要翻译：在具有通过形成在存储单元区域中的沟槽中的绝缘膜形成存储节点电极从而形成电容器的结构的DRAM中，并且其中存储节点电极连接在源极/漏极区域 MOSFET通过形成在绝缘膜的一部分中的存储节点接触，沟槽设置成在MOSFET的沟道区域中宽度偏离，使得相邻元件区域之间的距离减小，而不会导致在形成存储节点接触，从而提供小型化的高可靠性DRAM。此外，存储节点接触和沟槽可以形成为大尺寸。

4. 发明授权

US5164801A A P channel MIS type semiconductor device 失效
标题翻译： P通道MIS型半导体器件
公开(公告)号：US5164801A
公开(公告)日：1992-11-17
申请号：US790066
申请日：1991-11-12
申请人： Katsuhiko Hieda , Kazumasa Sunouchi , Akihiro Nitayama , Kazushi Tsuda , Hiroshi Takato , Naoko Takenouchi
发明人： Katsuhiko Hieda , Kazumasa Sunouchi , Akihiro Nitayama , Kazushi Tsuda , Hiroshi Takato , Naoko Takenouchi
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/823864 , H01L27/0623 , H01L27/092 , H01L29/78 , Y10S257/90
摘要： A P channel MIS type semiconductor device have P type source and drain regions formed in a N type semiconductor substrate. Each source and drain regions are constructed the low and high impurity concentration layers. Channel side edges of the low concentration impurity layers arranged inside of the high concentration impurity layers. These double layer source and drain structure prevent the off set gate construction and the parasitic resistance.
摘要翻译： P沟道MIS型半导体器件具有形成在N型半导体衬底中的P型源区和漏区。每个源极和漏极区域被构造为低和高杂质浓度层。低浓度杂质层的通道侧边缘布置在高浓度杂质层的内部。这些双层源极和漏极结构防止了闭合栅极结构和寄生电阻。

5. 发明授权

US5248628A Method of fabricating a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5248628A
公开(公告)日：1993-09-28
申请号：US896537
申请日：1992-06-09
申请人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
发明人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.
摘要翻译：一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔，在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料从而可以使存储器件的尺寸小并且可以提高可靠性。此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

6. 发明授权

US5144579A Semiconductor memory device and its fabricating method 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5144579A
公开(公告)日：1992-09-01
申请号：US578608
申请日：1990-09-07
申请人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
发明人： Naoko Okabe , Satoshi Inoue , Kazumasa Sunouchi , Takashi Yamada , Akihiro Nitayama , Hiroshi Takato
IPC分类号： H01L27/04 , H01L21/28 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.
摘要翻译：一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔，在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料从而可以使存储器件的尺寸小并且可以提高可靠性。此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

7. 发明授权

US06720606B1 Dynamic semiconductor memory device having a trench capacitor 失效
标题翻译：具有沟槽电容器的动态半导体存储器件
公开(公告)号：US06720606B1
公开(公告)日：2004-04-13
申请号：US09660390
申请日：2000-09-12
申请人： Akihiro Nitayama , Katsuhiko Hieda , Shigeru Ishibashi , Yusuke Kohyama
发明人： Akihiro Nitayama , Katsuhiko Hieda , Shigeru Ishibashi , Yusuke Kohyama
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10832 , H01L27/10861 , H01L27/10888 , H01L27/10894 , H01L29/945
摘要： A semiconductor memory device has a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitors having a trench extends through the first semiconductor region and the second semiconductor region, and is formed such that its top does not reach a top surface of the second semiconductor region, and the trench is formed therein with a conductive trench fill. A pair of gate electrodes is formed on the second semiconductor region, overlying the trench capacitor. A pair of insulating layers is formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers. The conductive layer has a leading end insulated from the second semiconductor region and reaching the interior of the second semiconductor region, and electrically connected to the conductive trench fill of the trench capacitor. A pair of third semiconductor regions of the first conduction type are formed in the second semiconductor region, and positioned opposite to each other with respect to the conductive layer. Each of the third semiconductor regions is directly in contact with the conductive layer, and constitutes either a source or a drain of transistors having one of the pair of gate electrodes, respectively. The pair of third semiconductor regions is formed substantially to a uniform depth.
摘要翻译：半导体存储器件具有形成在第一半导体区域上的半导体衬底，形成在半导体衬底上的第一导电类型的第一半导体区域，与第一导电类型相反的第二导电类型的第二半导体区域。具有沟槽的沟槽电容器延伸穿过第一半导体区域和第二半导体区域，并且形成为使得其顶部不到达第二半导体区域的顶表面，并且沟槽在其中形成有导电沟槽填充物。在第二半导体区上形成一对栅电极，覆盖在沟槽电容器上。形成一对绝缘层以覆盖该对栅电极中的每一个。在一对绝缘层之间形成导电层，以与一对绝缘层中的每一个自对准。导电层具有与第二半导体区域绝缘并到达第二半导体区域的内部的前端，并且电连接到沟槽电容器的导电沟槽填充物。第一导电类型的一对第三半导体区域形成在第二半导体区域中，并且相对于导电层彼此相对定位。第三半导体区域中的每一个直接与导电层接触，并且分别构成具有一对栅极电极之一的晶体管的源极或漏极。一对第三半导体区域基本上形成为均匀的深度。

8. 发明授权

US06236079B1 Dynamic semiconductor memory device having a trench capacitor 失效
标题翻译：具有沟槽电容器的动态半导体存储器件
公开(公告)号：US06236079B1
公开(公告)日：2001-05-22
申请号：US08982478
申请日：1997-12-02
申请人： Akihiro Nitayama , Katsuhiko Hieda
发明人： Akihiro Nitayama , Katsuhiko Hieda
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10832 , H01L27/10861 , H01L27/10888 , H01L27/10894 , H01L29/945
摘要： A semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. First, second, and third spaced apart bit lines are formed on the semiconductor substrate and extend in a second direction. An isolated active areas are formed on the semiconductor substrate under the second bit line. A first transfer gate transistor is formed in the active area, the first transfer gate transistor including spaced apart source and drain regions and the second word line being insulatively spaced from a channel region between the source and drain regions. A second transfer gate transistor is formed in the active area, the second transfer gate transistor including spaced apart source and drain regions and the third word line being insulatively spaced from a channel region between the source and drain regions. A first storage node is formed in a portion of the semiconductor substrate which is between the first and second word lines, between the first and second bit lines, under the second bit line, and between the second and third bit line. A second storage node is formed in a portion of the semiconductor substrate which is between the third and fourth word lines, between the first and second bit lines, under the second bit line, and between the second and third bit line.
摘要翻译：半导体存储器件包括半导体衬底和形成在半导体衬底上并沿第一方向延伸的第一，第二，第三和第四间隔开的字线。第一，第二和第三间隔开的位线形成在半导体衬底上并沿第二方向延伸。在第二位线下的半导体衬底上形成隔离的有源区。第一传输门晶体管形成在有源区中，第一传输栅极晶体管包括间隔开的源极和漏极区，并且第二字线与源极和漏极区之间的沟道区域间隔开。第二传输门晶体管形成在有源区中，第二传输栅极晶体管包括间隔开的源极和漏极区，并且第三字线与源区和漏区之间的沟道区域间隔开。第一存储节点形成在半导体衬底的位于第一和第二字线之间，第一位线和第二位线之间，第二位线下方以及第二位线和第三位线之间的部分中。第二存储节点形成在半导体衬底的位于第三和第四字线之间，第一位线和第二位线之间，第二位线之下以及第二位线和第三位线之间的部分中。

9. 发明授权

US06707706B2 Semiconductor memory device and method for manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06707706B2
公开(公告)日：2004-03-16
申请号：US10183156
申请日：2002-06-28
申请人： Akihiro Nitayama , Katsuhiko Hieda
发明人： Akihiro Nitayama , Katsuhiko Hieda
IPC分类号： G11C1124
CPC分类号： H01L27/10876 , H01L27/10817 , H01L27/10823 , H01L27/10885 , H01L27/10888 , H01L27/10891 , H01L28/90
摘要： A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.
摘要翻译：半导体存储器件包括形成在半导体衬底上的存储单元阵列区域中的多个柱状部分。柱状部分通过多个沟槽彼此隔离，并且这些沟槽具有深度不同的第一和第二底部。半导体器件包括多个单元晶体管，其包括形成在第一底部的第一扩散层区域，其比第二底部浅，形成在柱状部分的表面部分中的第二扩散层区域和多个栅电极邻近第一和第二扩散层区域并且沿着柱状部分的至少一个侧表面部分延伸。

10. 发明授权

US5350708A Method of making dynamic random access semiconductor memory device 失效
标题翻译：制作动态随机存取半导体存储器件的方法
公开(公告)号：US5350708A
公开(公告)日：1994-09-27
申请号：US77744
申请日：1993-06-18
申请人： Atsushi Yagishita , Katsuhiko Hieda , Akihiro Nitayama , Fumio Horiguchi
发明人： Atsushi Yagishita , Katsuhiko Hieda , Akihiro Nitayama , Fumio Horiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10841 , H01L27/10823
摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.
摘要翻译：在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。在槽的中心部分形成场氧化膜。在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元阵列是结构化的

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