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    • 9. 发明授权
    • Semiconductor device
    • 半导体器件
    • US09136388B2
    • 2015-09-15
    • US13549867
    • 2012-07-16
    • Shunpei YamazakiMasahiro TakahashiTatsuya HondaTakehisa Hatano
    • Shunpei YamazakiMasahiro TakahashiTatsuya HondaTakehisa Hatano
    • H01L29/26H01L29/786
    • H01L29/7869H01L29/24H01L29/78618
    • Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
    • 提供了能够实现所谓的常关断开关元件的晶体管的结构及其制造方法。 提供了通过提高晶体管的特性实现高速响应和高速操作的半导体器件的结构及其制造方法。 提供了一种高度可靠的半导体器件。 在其中半导体层,源极和漏极电极层,栅极绝缘层和栅极电极层以该顺序堆叠的晶体管中。 作为半导体层,含有铟,镓,锌和氧中的至少四种元素的氧化物半导体层,铟的组成比(原子百分比)为镓和a的组成比的两倍以上 使用锌的组成比。
    • 10. 发明授权
    • Resistance change memory
    • 电阻变化记忆
    • US09123412B2
    • 2015-09-01
    • US14018011
    • 2013-09-04
    • Masahiro TakahashiDong Keun KimHyuck Sang Yim
    • Masahiro TakahashiDong Keun KimHyuck Sang Yim
    • G11C11/00G11C13/00
    • G11C13/003G11C11/1659G11C11/1673G11C13/0004G11C13/0007G11C13/004G11C2013/0054
    • According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
    • 根据一个实施例,电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后,控制器接通第一和第二晶体管。