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1. 发明授权

US08498144B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08498144B2
公开(公告)日：2013-07-30
申请号：US13191678
申请日：2011-07-27
申请人： Masahiro Takahashi , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
发明人： Masahiro Takahashi , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
IPC分类号： G11C11/00 , G11C11/15
CPC分类号： G11C8/10 , G11C8/08 , G11C11/1675 , G11C11/1693
摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
摘要翻译：半导体存储装置包括第一至第四开关电路。半导体存储装置包括用于控制字线电压的行译码器。半导体存储装置包括控制端子连接到字线的第一选择晶体管。半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。半导体存储装置包括控制端子连接到字线的第二选择晶体管。半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

2. 发明授权

US08705270B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US08705270B2
公开(公告)日：2014-04-22
申请号：US13415662
申请日：2012-03-08
申请人： Masahiro Takahashi , Yoshihiro Ueda
发明人： Masahiro Takahashi , Yoshihiro Ueda
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.
摘要翻译：半导体存储器具有第一开关电路和第二开关电路。半导体存储器具有控制字线电压的行解码器。半导体存储器具有第一写入电路，该第一写入电路包括连接到第一开关电路的一端的第一信号端子，以输入和输出写入电流。半导体存储器具有第二写入电路，该第二写入电路包括连接到第二开关电路的一端的第二信号端子，以输入和输出写入电流。半导体存储器具有包括连接到字线的控制端的选择晶体管。半导体存储器具有与第一位线和第二位线之间的选择晶体管串联连接的电阻变化元件，并根据所施加的电流而变化电阻值。

3. 发明申请

US20120230090A1 SEMICONDUCTOR MEMORY 失效
标题翻译：半导体存储器
公开(公告)号：US20120230090A1
公开(公告)日：2012-09-13
申请号：US13415662
申请日：2012-03-08
申请人： Masahiro Takahashi , Yoshihiro Ueda
发明人： Masahiro Takahashi , Yoshihiro Ueda
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1675
摘要： A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current.
摘要翻译：半导体存储器具有第一开关电路和第二开关电路。半导体存储器具有控制字线电压的行解码器。半导体存储器具有第一写入电路，该第一写入电路包括连接到第一开关电路的一端的第一信号端子，以输入和输出写入电流。半导体存储器具有第二写入电路，该第二写入电路包括连接到第二开关电路的一端的第二信号端子，以输入和输出写入电流。半导体存储器具有包括连接到字线的控制端的选择晶体管。半导体存储器具有与第一位线和第二位线之间的选择晶体管串联连接的电阻变化元件，并且根据所施加的电流而改变电阻值。

4. 发明授权

US09911856B2 Semiconductor device 有权
公开(公告)号：US09911856B2
公开(公告)日：2018-03-06
申请号：US12900145
申请日：2010-10-07
申请人： Shunpei Yamazaki , Akiharu Miyanaga , Masahiro Takahashi , Hideyuki Kishida , Junichiro Sakata
发明人： Shunpei Yamazaki , Akiharu Miyanaga , Masahiro Takahashi , Hideyuki Kishida , Junichiro Sakata
IPC分类号： H01L29/786 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/42384 , H01L29/78606 , H01L29/78696
摘要： One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

5. 发明授权

US09635313B2 Information processing method and information processing system 有权
公开(公告)号：US09635313B2
公开(公告)日：2017-04-25
申请号：US13538560
申请日：2012-06-29
申请人： Yutaka Hasegawa , Yoichi Mizutani , Masato Kajimoto , Masahiro Takahashi , Hiroshi Kyusojin
发明人： Yutaka Hasegawa , Yoichi Mizutani , Masato Kajimoto , Masahiro Takahashi , Hiroshi Kyusojin
IPC分类号： H04N7/15 , G06F3/0484 , H04L12/18 , G06Q10/10 , H04L29/06 , G06F17/30
CPC分类号： G06F3/04845 , G06F3/1454 , G06F17/30056 , G06F2203/04803 , G06F2203/04806 , G06Q10/10 , H04L12/1813 , H04L12/1822 , H04L12/1827 , H04L65/403 , H04M2250/62 , H04N7/15
摘要： An information processing system and a method for operating same are provided. The information processing system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus is configured to display a first synchronous image in a first window, the first window having an operation right. The second information processing apparatus has a synchronous state or an asynchronous state. The second information processing apparatus is configured to: display a second synchronous image; in response to a first request, switch from the synchronous state to the asynchronous state; and in response to a second request, switch from the asynchronous state to the synchronous state.

6. 发明授权

US09627198B2 Method for manufacturing thin film semiconductor device 有权
公开(公告)号：US09627198B2
公开(公告)日：2017-04-18
申请号：US12894791
申请日：2010-09-30
申请人： Shunpei Yamazaki , Akiharu Miyanaga , Masahiro Takahashi , Hideyuki Kishida , Junichiro Sakata
发明人： Shunpei Yamazaki , Akiharu Miyanaga , Masahiro Takahashi , Hideyuki Kishida , Junichiro Sakata
IPC分类号： H01L21/00 , H01L21/84 , H01L21/02 , H01L29/786 , H01L27/12
CPC分类号： H01L21/02554 , G02F1/1368 , G02F1/167 , H01L21/02164 , H01L21/02172 , H01L21/02266 , H01L21/02422 , H01L21/02565 , H01L21/02631 , H01L21/477 , H01L27/1225 , H01L27/127 , H01L27/3262 , H01L29/24 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.

7. 发明授权

US09535834B2 Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit 有权
标题翻译：电子设备包括具有布置在字线驱动单元的不同侧上的可变电阻存储元件的存储器阵列
公开(公告)号：US09535834B2
公开(公告)日：2017-01-03
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G06F12/08 , G11C13/00 , G11C11/4099 , G11C11/16
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
摘要翻译：电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压阵列第一读取控制单元; 和第二读取控制单元。

8. 发明授权

US09484091B2 Resistance change memory 有权
公开(公告)号：US09484091B2
公开(公告)日：2016-11-01
申请号：US14636740
申请日：2015-03-03
申请人： Masahiro Takahashi , Akira Katayama , Dong Keun Kim , Byoung Chan Oh
发明人： Masahiro Takahashi , Akira Katayama , Dong Keun Kim , Byoung Chan Oh
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/00 , G11C13/0026 , G11C13/0061 , G11C2013/0045 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.

9. 发明授权

US09398233B2 Processing apparatus, system, method and program for processing information to be shared 有权
标题翻译：用于处理要共享的信息的处理装置，系统，方法和程序
公开(公告)号：US09398233B2
公开(公告)日：2016-07-19
申请号：US13880267
申请日：2012-07-10
申请人： Hiroshi Kyusojin , Yoichi Mizutani , Yutaka Hasegawa , Masahiro Takahashi
发明人： Hiroshi Kyusojin , Yoichi Mizutani , Yutaka Hasegawa , Masahiro Takahashi
IPC分类号： G06K9/00 , H04N5/265 , H04N7/15 , H04M3/56 , G06F19/00 , H04L12/18
CPC分类号： H04N5/265 , G06F19/00 , G06F19/321 , G16H80/00 , H04L12/1827 , H04M3/567 , H04N7/15
摘要： An information processing apparatus, an information processing system, and a method of processing information are provided. In one embodiment, the information processing apparatus includes a processor, and a memory device storing instructions. When executed by the processor, the instructions cause the processor to receive, from a first information processing apparatus, area specifying information and location information, the area specifying information specifying a display area in an image, the display area including a plurality of partial images, the location information indicating at least one location of the plurality of partial images. The instructions further cause the processor to transmit, to a second information processing apparatus, the area specifying information and the location information.
摘要翻译：提供信息处理装置，信息处理系统和处理信息的方法。在一个实施例中，信息处理设备包括处理器和存储指令的存储器件。当处理器执行时，指令使得处理器从第一信息处理设备接收区域指定信息和位置信息，区域指定信息指定图像中的显示区域，显示区域包括多个部分图像，所述位置信息指示所述多个部分图像中的至少一个位置。所述指令还使所述处理器向所述第二信息处理设备发送所述区域指定信息和所述位置信息。

10. 发明授权

US09308602B2 Laser lap welding method 有权
标题翻译：激光搭接焊接方法
公开(公告)号：US09308602B2
公开(公告)日：2016-04-12
申请号：US13333349
申请日：2011-12-21
申请人： Kazuhiro Hayashimoto , Yuta Fujinuma , Tsukasa Hagihara , Shuichi Usui , Yoshitaka Sanuki , Masahiro Takahashi
发明人： Kazuhiro Hayashimoto , Yuta Fujinuma , Tsukasa Hagihara , Shuichi Usui , Yoshitaka Sanuki , Masahiro Takahashi
IPC分类号： B23K26/28 , B23K26/32
CPC分类号： B23K26/28 , B23K26/082 , B23K26/244 , B23K26/32 , B23K26/322 , B23K2101/006 , B23K2101/18 , B23K2101/34 , B23K2103/04 , B23K2103/08 , B23K2103/50
摘要： A laser lap welding method by irradiating of a laser beam from one side of a plurality of overlapped workpieces (1, 2), the method includes the steps of: scanning (La) the laser beam in the forward direction along a predetermined section of the workpieces; reversing the scanning direction of the laser beam at a terminating end (t) of the predetermined section; scanning (Lb) the laser beam in the backward direction and terminating of the irradiating of the laser beam onto the predetermined section, wherein the scanning of the laser beam in the backward direction is offset from the scanning of the laser beam in the forward direction such that a part of weld bead (12) formed by the laser scanning in the backward direction overlaps the weld bead (11) formed by the laser scan in the forward direction.
摘要翻译：一种通过从多个重叠工件（1,2）的一侧照射激光束的激光搭接焊接方法，所述方法包括以下步骤：沿着向前方向沿着预定部分扫描（La）激光束工件在所述预定部分的终止端（t）反转所述激光束的扫描方向; 沿着反方向扫描（Lb）激光束并终止将激光束照射到预定部分上，其中激光束沿向后方向的扫描偏离激光束在向前方向上的扫描，例如通过沿向后方向的激光扫描形成的焊道（12）的一部分与沿着向前方向的激光扫描形成的焊道（11）重叠。

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