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1. 发明申请

US20160133308A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20160133308A1
公开(公告)日：2016-05-12
申请号：US14988144
申请日：2016-01-05
申请人： Katsuyuki FUJITA
发明人： Katsuyuki FUJITA
IPC分类号： G11C11/16 , G11C29/44
CPC分类号： G11C11/1675 , G06F11/00 , G06F11/3037 , G06F11/3058 , G11C7/04 , G11C7/08 , G11C7/1006 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C13/004 , G11C13/0069 , G11C16/26 , G11C29/44 , G11C2013/0052 , G11C2013/0092 , G11C2029/0411
摘要： A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information.
摘要翻译：电阻变化存储器包括存储单元阵列，其包括包括磁性隧道结（MTJ）元件的存储单元; 写入和读取电路，用于对存储器单元执行写入操作和读取操作; 温度传感器，其输出与存储单元阵列的温度对应的温度信息; 以及存储器控制器，其响应于温度信息控制写入和读取电路的写入操作和读取操作，使得从写入命令输入到预充电命令输入的第一时间段根据温度而变化信息，而从活动命令输入到预充电命令输入的第二时间段不管温度信息如何都是固定的。

2. 发明申请

US20150262639A1 RESISTANCE CHANGE MEMORY 有权
标题翻译：电阻变化记忆
公开(公告)号：US20150262639A1
公开(公告)日：2015-09-17
申请号：US14482904
申请日：2014-09-10
申请人： Katsuyuki FUJITA
发明人： Katsuyuki FUJITA
IPC分类号： G11C11/16 , G11C29/44
CPC分类号： G11C11/1675 , G06F11/00 , G06F11/3037 , G06F11/3058 , G11C7/04 , G11C7/08 , G11C7/1006 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C13/004 , G11C13/0069 , G11C16/26 , G11C29/44 , G11C2013/0052 , G11C2013/0092 , G11C2029/0411
摘要： According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，写入和读取电路，温度传感器和存储器控制器。存储单元阵列包括包括磁性隧道结（MTJ）元件的存储单元。写入和读取电路对存储器单元执行写入操作和读取操作。温度传感器输出与存储单元阵列的温度对应的温度信息。存储器控制器根据温度信息控制写入和读取电路的写入操作和读取操作。

3. 发明授权

US09025400B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09025400B2
公开(公告)日：2015-05-05
申请号：US13601037
申请日：2012-08-31
申请人： Katsuyuki Fujita , Katsuhiko Hoya
发明人： Katsuyuki Fujita , Katsuhiko Hoya
IPC分类号： G11C11/16 , G11C8/18 , G11C7/22
CPC分类号： G11C11/1693 , G11C7/222 , G11C8/18 , G11C11/16 , G11C11/1653 , G11C11/1673
摘要： A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.
摘要翻译：根据本实施例的半导体存储装置包括分别包括多个存储单元的多个存储单元。数据总线由存储器单元共享并从存储器单元或存储器单元传送数据。定时控制器包括由共享数据总线的存储器单元共享的延迟时间单元。定时控制器被配置为在接收到输入信号之后经过预定的延迟时间之后输出用于驱动存储器单元的控制信号。

4. 发明申请

US20140286086A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140286086A1
公开(公告)日：2014-09-25
申请号：US14014183
申请日：2013-08-29
申请人： Katsuyuki FUJITA
发明人： Katsuyuki FUJITA
IPC分类号： G11C11/16
CPC分类号： G11C29/76 , G11C11/161 , G11C11/1653 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C29/04 , G11C29/787
摘要： According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.
摘要翻译：根据一个实施例，半导体存储器件包括连接到存储单元阵列的第一字线，连接到冗余区的第二字线，配置为基于行地址从第一字线执行选择的第一行解码器，判断电路，被配置为基于包括在行地址中的冗余地址来确定是否需要具有冗余区域的替换操作;以及第二行解码器，被配置为执行从第二字线的选择。行地址包括在分时方法中按顺序输入的第一行地址和第二行地址。第一行地址包括所有冗余地址。

5. 发明授权

US08498145B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08498145B2
公开(公告)日：2013-07-30
申请号：US13205094
申请日：2011-08-08
申请人： Katsuyuki Fujita , Yoshihiro Ueda
发明人： Katsuyuki Fujita , Yoshihiro Ueda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C5/025 , G11C7/14 , G11C8/08 , G11C11/1659 , G11C11/1675
摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
摘要翻译：存储器包括连接在第一和第二BL之间的位线，字线和存储单元。布置在BL的延伸方向上的单元构成列。第二个BL在两列之间共享。第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。该装置包括与相邻存储元件具有相等距离的虚拟单元。此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。每个单元包含选择晶体管。选择晶体管并联连接在存储元件和第一BL之间。晶体管的栅极连接到不同的WL。

6. 发明申请

US20130107638A1 SEMICONDUCTOR STORAGE DEVICE 有权
公开(公告)号：US20130107638A1
公开(公告)日：2013-05-02
申请号：US13601037
申请日：2012-08-31
申请人： Katsuyuki FUJITA , Katsuhiko HOYA
发明人： Katsuyuki FUJITA , Katsuhiko HOYA
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C11/1693 , G11C7/222 , G11C8/18 , G11C11/16 , G11C11/1653 , G11C11/1673
摘要： A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.

7. 发明授权

US08369129B2 Semiconductor memory device with variable resistance element 有权
标题翻译：具有可变电阻元件的半导体存储器件
公开(公告)号：US08369129B2
公开(公告)日：2013-02-05
申请号：US12818028
申请日：2010-06-17
申请人： Katsuyuki Fujita , Kenji Tsuchida
发明人： Katsuyuki Fujita , Kenji Tsuchida
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C2013/0054
摘要： According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
摘要翻译：根据一个实施例，半导体存储器件包括可变电阻元件，其被配置为根据电阻值的变化来存储数据0和数据1;电流发生器，被配置为产生用于确定可变电阻元件的数据的参考电流;以及在存储数据0的可变电阻元件的导纳与存储数据1的可变电阻元件的导纳之间的导纳中心处的导纳和感测放大器包括连接到可变电阻元件的第一输入端子和连接到可变电阻元件的第二输入端子电流发生器，并且被配置为比较第一输入端子和第二输入端子的电流。

8. 发明申请

US20130029257A1 THERMOCHROMIC COLOR-MEMORIZATION TONER, CARTRIDGE INCLUDING SAME HOUSED THEREIN, IMAGE FORMATION APPARATUS, CARTRIDGE SET, AND IMAGE FORMATION APPARATUS SET 有权
标题翻译：热变色彩记忆墨粉盒，包括同类住房的图像，图像形成装置，墨盒和图像形成装置
公开(公告)号：US20130029257A1
公开(公告)日：2013-01-31
申请号：US13509663
申请日：2009-11-13
申请人： Katsuyuki Fujita , Yoshiaki Ono , Yutaka Shibahashi
发明人： Katsuyuki Fujita , Yoshiaki Ono , Yutaka Shibahashi
IPC分类号： G03G9/00 , G03G15/08
CPC分类号： G03G9/0812 , C09D11/17 , G03G9/0821 , G03G9/0825 , G03G9/0926 , G03G9/0928
摘要： The present invention relates to a thermochromic color-memory toner containing: a microcapsule pigment encapsulating a thermochromic color-memory composition; and a binder resin, in which the microcapsule pigment shows a hysteresis characteristic that, in a temperature-rise process, decoloration starts when the temperature reaches t3 and the pigment completely reaches a decolored state in a temperature region of t4 or higher, and in a temperature-drop process, coloration starts when the temperature reaches t2 and the pigment completely reaches a colored state in a temperature region of ti or lower, and ti is in a range of from −50 to 0° C. and t4 is in a range of from 50 to 150° C.
摘要翻译：本发明涉及一种热致变色彩记忆调色剂，其含有：包封热变色色记忆组合物的微胶囊颜料; 和粘合剂树脂，其中微胶囊颜料显示出在温度升高过程中当温度达到t3时开始脱色并且颜料在t4或更高的温度区域完全达到脱色状态的滞后特性，并且在温度下降过程中，当温度达到t2时开始着色，并且颜料在ti或更低的温度区域中完全达到着色状态，并且t 1在-50至0℃的范围内，并且t 4在一定范围内为50〜150℃

9. 发明授权

US08173052B2 Writing implement with thermochromic coloring color-memory composition 有权
标题翻译：书写工具用热致色色彩记忆组合
公开(公告)号：US08173052B2
公开(公告)日：2012-05-08
申请号：US12846238
申请日：2010-07-29
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： B05C21/00 , B43K7/00 , B43L19/00 , G02F1/361
CPC分类号： B41M5/305 , B41M5/165 , B41M5/3375 , C09B67/0013 , C09D5/26 , C09D11/037 , C09D11/17 , C09D11/18 , C09K9/02 , C09K2211/1014
摘要： A writing implement with a thermochromic coloring color-memory composition which comprises a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) a reaction medium which controls color reactions of the components (A) and (B), wherein a complete decoloring temperature (T4) of the thermochromic coloring color-memory composition is 50° C. or higher and a coloring starting temperature (T2) of thermochromic coloring color-memory composition is 10° C. or lower regarding the color density-temperature curve, and the thermochromic coloring color-memory composition has color-memory ability at the ordinary temperature range.
摘要翻译：一种具有热致变色着色记录组合物的书写工具，其包含（A）电子给体着色有机化合物，（B）电子接受化合物和（C）控制组分的着色反应的反应介质的均匀溶解混合物（（A）和（B），其中，所述热致变色着色色记忆组合物的完全脱色温度（T4）为50℃以上，所述着色着色色记忆组合物的着色开始温度（T2）为10℃。或更低，并且热致变色着色色记忆组合物在常温范围内具有记忆能力。

10. 发明申请

US20120063216A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120063216A1
公开(公告)日：2012-03-15
申请号：US13205094
申请日：2011-08-08
申请人： Katsuyuki Fujita , Yoshihiro Ueda
发明人： Katsuyuki Fujita , Yoshihiro Ueda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C5/025 , G11C7/14 , G11C8/08 , G11C11/1659 , G11C11/1675
摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
摘要翻译：存储器包括连接在第一和第二BL之间的位线，字线和存储单元。布置在BL的延伸方向上的单元构成列。第二个BL在两列之间共享。第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。该装置包括与相邻存储元件具有相等距离的虚拟单元。此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。每个单元包括选择晶体管。选择晶体管并联连接在存储元件和第一BL之间。晶体管的栅极连接到不同的WL。

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