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1. 发明授权

US08498144B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US08498144B2
公开(公告)日：2013-07-30
申请号：US13191678
申请日：2011-07-27
申请人： Masahiro Takahashi , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
发明人： Masahiro Takahashi , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
IPC分类号： G11C11/00 , G11C11/15
CPC分类号： G11C8/10 , G11C8/08 , G11C11/1675 , G11C11/1693
摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
摘要翻译：半导体存储装置包括第一至第四开关电路。半导体存储装置包括用于控制字线电压的行译码器。半导体存储装置包括控制端子连接到字线的第一选择晶体管。半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。半导体存储装置包括控制端子连接到字线的第二选择晶体管。半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

2. 发明申请

US20120063215A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20120063215A1
公开(公告)日：2012-03-15
申请号：US13191678
申请日：2011-07-27
申请人： Masahiro TAKAHASHI , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
发明人： Masahiro TAKAHASHI , Katsuyuki Fujita , Yoshihiro Ueda , Katsuhiko Hoya
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/1675 , G11C11/1693
摘要： A semiconductor storage device includes first to fourth switch circuit. The semiconductor storage device includes a row decoder which controls a voltage of a word line. The semiconductor storage device includes a first selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a first resistance change element which is connected in series to the first selection transistor between the first bit line and the second bit line, and of which a resistance value changes according to a flowing current. The semiconductor storage device includes a second selection transistor of which a control terminal is connected to the word line. The semiconductor storage device includes a second resistance change element which is connected in series to the second selection transistor between the second bit line and the third bit line, and of which a resistance value changes according to a flowing current.
摘要翻译：半导体存储装置包括第一至第四开关电路。半导体存储装置包括用于控制字线电压的行译码器。半导体存储装置包括控制端子连接到字线的第一选择晶体管。半导体存储装置包括与第一位线和第二位线之间的第一选择晶体管串联连接的第一电阻变化元件，其电阻值根据流动电流而变化。半导体存储装置包括控制端子连接到字线的第二选择晶体管。半导体存储装置包括与第二位线和第三位线之间的第二选择晶体管串联连接的第二电阻变化元件，其电阻值根据流动电流而变化。

3. 发明授权

US09025400B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09025400B2
公开(公告)日：2015-05-05
申请号：US13601037
申请日：2012-08-31
申请人： Katsuyuki Fujita , Katsuhiko Hoya
发明人： Katsuyuki Fujita , Katsuhiko Hoya
IPC分类号： G11C11/16 , G11C8/18 , G11C7/22
CPC分类号： G11C11/1693 , G11C7/222 , G11C8/18 , G11C11/16 , G11C11/1653 , G11C11/1673
摘要： A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.
摘要翻译：根据本实施例的半导体存储装置包括分别包括多个存储单元的多个存储单元。数据总线由存储器单元共享并从存储器单元或存储器单元传送数据。定时控制器包括由共享数据总线的存储器单元共享的延迟时间单元。定时控制器被配置为在接收到输入信号之后经过预定的延迟时间之后输出用于驱动存储器单元的控制信号。

4. 发明授权

US08498145B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08498145B2
公开(公告)日：2013-07-30
申请号：US13205094
申请日：2011-08-08
申请人： Katsuyuki Fujita , Yoshihiro Ueda
发明人： Katsuyuki Fujita , Yoshihiro Ueda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C5/025 , G11C7/14 , G11C8/08 , G11C11/1659 , G11C11/1675
摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
摘要翻译：存储器包括连接在第一和第二BL之间的位线，字线和存储单元。布置在BL的延伸方向上的单元构成列。第二个BL在两列之间共享。第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。该装置包括与相邻存储元件具有相等距离的虚拟单元。此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。每个单元包含选择晶体管。选择晶体管并联连接在存储元件和第一BL之间。晶体管的栅极连接到不同的WL。

5. 发明申请

US20120063216A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120063216A1
公开(公告)日：2012-03-15
申请号：US13205094
申请日：2011-08-08
申请人： Katsuyuki Fujita , Yoshihiro Ueda
发明人： Katsuyuki Fujita , Yoshihiro Ueda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C5/025 , G11C7/14 , G11C8/08 , G11C11/1659 , G11C11/1675
摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
摘要翻译：存储器包括连接在第一和第二BL之间的位线，字线和存储单元。布置在BL的延伸方向上的单元构成列。第二个BL在两列之间共享。第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。该装置包括与相邻存储元件具有相等距离的虚拟单元。此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。每个单元包括选择晶体管。选择晶体管并联连接在存储元件和第一BL之间。晶体管的栅极连接到不同的WL。

6. 发明授权

US09257167B2 Resistance change memory 有权
标题翻译：电阻变化记忆
公开(公告)号：US09257167B2
公开(公告)日：2016-02-09
申请号：US14482904
申请日：2014-09-10
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C11/16 , G11C11/14 , G11C7/04 , G11C11/02 , G11C29/44 , G11C11/56 , G11C7/08 , G11C16/26 , G11C13/00 , G11C29/04
CPC分类号： G11C11/1675 , G06F11/00 , G06F11/3037 , G06F11/3058 , G11C7/04 , G11C7/08 , G11C7/1006 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C11/5607 , G11C13/004 , G11C13/0069 , G11C16/26 , G11C29/44 , G11C2013/0052 , G11C2013/0092 , G11C2029/0411
摘要： According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，写入和读取电路，温度传感器和存储器控制器。存储单元阵列包括包括磁性隧道结（MTJ）元件的存储单元。写入和读取电路对存储器单元执行写入操作和读取操作。温度传感器输出与存储单元阵列的温度对应的温度信息。存储器控制器根据温度信息控制写入和读取电路的写入操作和读取操作。

7. 发明授权

US08947918B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08947918B2
公开(公告)日：2015-02-03
申请号：US14014231
申请日：2013-08-29
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1653 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，被配置为保持输入到输入/输出电路的数据并保持从存储单元阵列读取的数据的缓冲器以及被配置为接收第一命令和来自外部的地址，并且响应于第一命令从耦合到由该地址指定的所选字线的存储器单元组读取数据到缓冲器。控制器接收在第一命令之后输入的第二命令，并且指示包括写入命令和/或读取命令的一组命令的最后命令，并响应于第二命令从缓冲器开始到存储器单元阵列的写入操作命令。

8. 发明授权

US08282299B2 Friction body, writing instrument and writing instrument set 有权
标题翻译：摩擦体，书写工具和书写工具组
公开(公告)号：US08282299B2
公开(公告)日：2012-10-09
申请号：US11946071
申请日：2007-11-28
申请人： Yoshihiro Ito , Shouichi Ohkawa , Katsuyuki Fujita
发明人： Yoshihiro Ito , Shouichi Ohkawa , Katsuyuki Fujita
IPC分类号： B43K29/00
CPC分类号： B43K29/02 , B43K1/086 , B43K7/02 , B43K7/10 , B43K8/04 , B43K8/06 , B43K23/12 , B43K23/126 , B43L19/0025 , B43L19/0068 , C09D11/16 , C09D11/18 , C09D11/50
摘要： A friction body that produces frictional heat allowing development, disappearance or change of color of handwriting formed with a writing instrument for producing thermochromic handwriting, with the friction body having a friction coefficient of 0.2 to 1.0 when rubbed against paper surface, and a writing instrument for use in forming thermochromic handwriting which is equipped with the friction body and a writing instrument set including the friction body and a writing instrument for use in forming thermochromic handwriting.
摘要翻译：产生摩擦热的摩擦体，其允许由用于产生热变色手写的书写工具形成的笔迹的显影，消失或变化，摩擦体摩擦纸面摩擦系数为0.2至1.0;以及书写工具用于形成配备有摩擦体的热变色手写体和包括摩擦体的书写工具组和用于形成热变色手写的书写工具。

9. 发明授权

US07675793B2 Semiconductor memory device and driving method for the device 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07675793B2
公开(公告)日：2010-03-09
申请号：US12033258
申请日：2008-02-19
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： This disclosure concerns a semiconductor memory device comprising: memory cells including floating bodies storing data; word lines connected to gates of the memory cells; a bit line pair connected to the memory cells and transmitting data stored in the memory cells; a sense node pair connected to the bit line pair and transmitting data stored in the memory cells; transfer gates connected between the bit line pair and the sense node pair; latch circuits latching a high-level potential in one sense node of the sense node pair, and latching a first low-level potential in the other sense node of the sense node pair; and a level shifter applying a second low-level potential lower than the first low-level potential to one bit line of the bit line pair according to the electric potentials latched in the sense node pair at the time of writing data or writing back data.
摘要翻译：本公开涉及一种半导体存储器件，包括：存储单元，其包括存储数据的浮动体; 连接到存储器单元的门的字线; 连接到存储器单元并发送存储在存储单元中的数据的位线对; 感测节点对，连接到所述位线对并发送存储在所述存储单元中的数据; 连接在位线对和感测节点对之间的传输门; 锁存电路锁存感测节点对的一个感测节点中的高电平电位，并且锁存感测节点对的另一个感测节点中的第一低电平电位; 以及电平移位器，根据在写入数据或写入数据时锁存在感测节点对中的电位，将比第一低电平电位低的第二低电平电位施加到位线对的一个位线。

10. 发明授权

US07539069B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07539069B2
公开(公告)日：2009-05-26
申请号：US11748187
申请日：2007-05-14
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/065 , G11C7/12 , G11C11/404 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2211/4016
摘要： This disclosure concerns a memory comprising a memory cell; a first and a second sense nodes transmitting the data on the first and the second bit lines which transmits data with reversed polarities from each other; a first transfer gate provided between the first bit line and the first sense node; a second transfer gate provided between the second bit line and the second sense node; a latch circuit provided between the first and the second sense nodes; a write signal line activated when the data is written or restore to the cell; and a gate circuit connecting the write signal line to the first bit line and the first sense node to the second bit line, or connecting the write signal line to the second bit line and the second sense node to the first bit line, when the data is written or restore.
摘要翻译：本公开涉及包括存储器单元的存储器; 第一和第二感测节点，以相反极性传输数据的第一和第二位线发送数据; 设置在第一位线和第一感测节点之间的第一传送门; 提供在第二位线和第二感测节点之间的第二传输门; 设置在第一和第二感测节点之间的锁存电路; 当数据被写入或恢复到单元时，写入信号线被激活; 以及门电路，其将所述写信号线与所述第一位线和所述第一感测节点连接到所述第二位线，或者当所述数据与所述第一位线连接时，将所述写入信号线连接到所述第二位线和所述第二感测节点到所述第一位线是写或还原。

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