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1. 发明授权

US08051268B2 Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method 失效
标题翻译：内存控制器，非易失性存储设备，非易失性存储系统和非易失性存储器地址管理方法
公开(公告)号：US08051268B2
公开(公告)日：2011-11-01
申请号：US11814202
申请日：2006-07-21
申请人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
发明人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7211
摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
摘要翻译：对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。逻辑地址范围分别与物理区域（段）相关联以管理地址。逻辑地址范围的大小相等。对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑地址范围和物理区域被分配。或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

2. 发明申请

US20090055618A1 MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD 失效
标题翻译：存储器控制器，非易失性存储设备，非易失性存储系统和非易失性存储器地址管理方法
公开(公告)号：US20090055618A1
公开(公告)日：2009-02-26
申请号：US11814202
申请日：2006-07-21
申请人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
发明人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7211
摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
摘要翻译：对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。逻辑地址范围分别与物理区域（段）相关联以管理地址。逻辑地址范围的大小相等。对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑地址范围和物理区域被分配。或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

3. 发明申请

US20080168252A1 Memory Controller, Nonvolatile Storage Device, Nonvolatile Storage System, and Memory Control Method 有权
标题翻译：存储控制器，非易失存储设备，非易失存储系统和存储器控制方法
公开(公告)号：US20080168252A1
公开(公告)日：2008-07-10
申请号：US11914989
申请日：2006-05-18
申请人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
发明人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： The invention presents a memory controller capable of shortening the creation time of address management table at the time of initialization of memory card, while avoiding decline of access speed due to process of writing back the address management table in normal operation.The memory controller 114 includes a read-write memory 113 for temporarily storing the address management table 112, a memory control unit 122 for writing, in a nonvolatile memory 115, an address management table temporarily stored in the read-write memory and address range specifying information for specifying the changeover destination address range, when the physical block of data writing destination is changed over from a certain address range to other address range, and an address management table generation unit 107 for reading out the distributed management information used for managing the state of physical block included in the address range specified based on the address range specifying information at the time of initialization, and generating the address management table 112 based on the distributed management information being read out.
摘要翻译：本发明提出了一种能够缩短存储卡初始化时的地址管理表的创建时间的存储器控制器，同时避免由于在正常操作中写入地址管理表的过程而导致的访问速度的下降。存储器控制器114包括用于临时存储地址管理表112的读写存储器113，用于在非易失性存储器115中写入临时存储在读写存储器中的地址管理表和指定地址范围的存储器控制单元122 用于指定切换目的地地址范围的信息，当数据写入目的地的物理块从特定地址范围改变到其他地址范围时，以及地址管理表生成单元107，用于读出用于管理状态的分布式管理信息包括在基于初始化时的地址范围指定信息指定的地址范围内的物理块，并且基于被读出的分布式管理信息生成地址管理表112。

4. 发明授权

US08051270B2 Memory controller, nonvolatile storage device, nonvolatile storage system, and memory control method 有权
标题翻译：内存控制器，非易失性存储设备，非易失性存储系统和存储器控制方法
公开(公告)号：US08051270B2
公开(公告)日：2011-11-01
申请号：US11914989
申请日：2006-05-18
申请人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
发明人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A memory controller for reducing a time to create an address management table during initialization of a memory card. The memory controller includes a read-write memory for temporarily storing the address management table and a second memory controller for writing, in a nonvolatile memory, an address management table temporarily stored in the read-write memory. The second memory controller also writes address range specifying information that specifies an address range, when a data writing destination is changed from a first address range to a second address range. The memory controller includes an address management table generator for reading distributed management information used for managing a state of at least one physical block included in the destination address range specified by the address range specifying information during initialization, and to generate the address management table based on the distributed management information.
摘要翻译：一种用于在存储卡初始化期间减少创建地址管理表的时间的存储器控制器。存储器控制器包括用于临时存储地址管理表的读写存储器和用于在非易失性存储器中写入临时存储在读写存储器中的地址管理表的第二存储器控制器。当数据写入目的地从第一地址范围改变到第二地址范围时，第二存储器控制器还写入指定地址范围的地址范围指定信息。存储器控制器包括地址管理表发生器，用于读取用于管理初始化期间由地址范围指定信息指定的目的地地址范围中包括的至少一个物理块的状态的分布式管理信息，并且基于分布式管理信息。

5. 发明授权

US08327068B2 Memory module, memory controller, nonvolatile storage, nonvolatile storage system, and memory read/write method 失效
标题翻译：内存模块，内存控制器，非易失性存储，非易失性存储系统和内存读/写方式
公开(公告)号：US08327068B2
公开(公告)日：2012-12-04
申请号：US11817532
申请日：2006-03-01
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue , Masayuki Toyama , Kunihiro Maki
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue , Masayuki Toyama , Kunihiro Maki
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , G06F11/1666 , G06F12/0246 , G06F2212/7201
摘要： In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.
摘要翻译：在具有破坏性读取类型的非易失性RAM的存储器中，归因于从非易失性RAM读取的数据的修复数量减少，并且存储器的总体寿命延长。在具有破坏性读取类型的非易失性RAM和易失性RAM的存储器中，并且在非易失性和易失性RAM中保持相同的数据，在读取时从易失性RAM中读出数据，并将数据写入易失性和非易失性RAM两者中。

6. 发明申请

US20090210612A1 MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM 审中-公开
标题翻译：内存控制器，非易失性存储器件和非易失性存储器系统
公开(公告)号：US20090210612A1
公开(公告)日：2009-08-20
申请号：US12282693
申请日：2007-03-12
申请人： Masahiro Nakanishi , Masayuki Toyama , Yutaka Nakamura , Yasushi Gohou , Masanori Matsuura , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shunichi Iwanari , Shinichi Tokumitsu
发明人： Masahiro Nakanishi , Masayuki Toyama , Yutaka Nakamura , Yasushi Gohou , Masanori Matsuura , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shunichi Iwanari , Shinichi Tokumitsu
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed.
摘要翻译：在逻辑扇区的重写处理中，传送的逻辑扇区的数据被临时存储在存储缓冲器中。当缓冲存储器已经完全填满数据时，数据被写入闪存。在包括具有大于来自外部的最小写入单位（扇区）的容量的写入单元（页）的闪存的重写处理中，可以减少撤离处理的执行次数并且可以执行快速数据重写。因此，可以使以扇区为单位重写的旧数据的撤离处理合理化，并提高数据重写速度。

7. 发明申请

US20090055576A1 MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD 有权
标题翻译：存储器控制器，非易失存储器件，非易失性存储系统和数据写入方法
公开(公告)号：US20090055576A1
公开(公告)日：2009-02-26
申请号：US11908715
申请日：2006-03-09
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Yutaka Nakamura , Masayuki Toyama , Yasushi Goho , Syunichi Iwanari , Yoshihisa Kato , Manabu Inoue
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Yutaka Nakamura , Masayuki Toyama , Yasushi Goho , Syunichi Iwanari , Yoshihisa Kato , Manabu Inoue
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/0656 , G06F3/0613 , G06F3/0619 , G06F3/0643 , G06F3/0679 , G06F12/0246 , G06F2212/1016 , G06F2212/7203
摘要： A nonvolatile storage device is provided with a nonvolatile main storage memory (114) whose erase size is larger than a cluster size, and a buffer (106), i.e. a nonvolatile auxiliary storage memory. At the time of writing data in the memory, the data is temporarily stored in the buffer (106), then, a plurality of data in the buffer (106) are collectively taken out to be stored in the main storage memory (114). Data in an original block is saved in a write block in the main storage memory. Thus, the data can be written in the main storage memory (114) at a high speed.
摘要翻译：非易失性存储装置具有擦除大小大于簇大小的非易失性主存储存储器（114）和缓冲器（106），即非易失性辅助存储存储器。在将数据写入存储器时，将数据临时存储在缓冲器（106）中，然后将缓冲器（106）中的多个数据集中取出以存储在主存储器（114）中。原始块中的数据保存在主存储器中的写入块中。因此，可以高速地将数据写入主存储存储器（114）。

8. 发明授权

US07475185B2 Nonvolatile memory system, nonvolatile memory device, memory controller, access device, and method for controlling nonvolatile memory device 有权
标题翻译：非易失性存储器系统，非易失性存储器件，存储器控制器，存取器件以及用于控制非易失性存储器件的方法
公开(公告)号：US07475185B2
公开(公告)日：2009-01-06
申请号：US11280810
申请日：2005-11-17
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shouichi Tsujita , Takuji Maeda , Shinji Inoue , Manabu Inoue , Masayuki Toyama , Keisuke Sakai
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Shouichi Tsujita , Takuji Maeda , Shinji Inoue , Manabu Inoue , Masayuki Toyama , Keisuke Sakai
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F3/0643 , G06F3/0613 , G06F3/0679
摘要： When a file system control part 155A writes file data into a main memory 142, a file can be easily written continuously and the number of file copy can be decreased at updating a directory entry by writing the file data and a directory entry into different allocation units. In this manner, when using a nonvolatile memory in which physical block size as an erase unit is larger than cluster size, the write performance can be enhanced.
摘要翻译：当文件系统控制部分155A将文件数据写入主存储器142时，可以容易地连续地写入文件，并且可以通过将文件数据和目录条目写入不同的分配单元来更新目录条目来减少文件拷贝的数量。以这种方式，当使用物理块大小作为擦除单位的非易失性存储器大于簇大小时，可以提高写入性能。

9. 发明授权

US07360012B2 Semiconductor memory device including memory controller for transmitting writing rate information to memory access device 有权
标题翻译：半导体存储器件包括用于将写入速率信息发送到存储器存取器件的存储器控制器
公开(公告)号：US07360012B2
公开(公告)日：2008-04-15
申请号：US11048046
申请日：2005-02-02
申请人： Kazuaki Tamura , Tomoaki Izumi , Tetsushi Kasahara , Masahiro Nakanishi , Kiminori Matsuno , Takuji Maeda
发明人： Kazuaki Tamura , Tomoaki Izumi , Tetsushi Kasahara , Masahiro Nakanishi , Kiminori Matsuno , Takuji Maeda
IPC分类号： G06F12/00 , G06K17/00 , G06K19/07
CPC分类号： G06F12/0246 , G11C2029/0409
摘要： A semiconductor memory card 1 includes a user data area 21 and a management information area 22, in a data storing unit 2. According to a writing test command from a memory access device 6, a memory controller 3 writes data into a user data storing area and measures the writing rate, and transmits the measurement result to the memory access device 6 via a host interface unit 4. Thereby, the memory access device 6 can recognize the writing rate.
摘要翻译：在数据存储单元2中，半导体存储卡1包括用户数据区21和管理信息区22。根据来自存储器访问装置6的写入测试命令，存储器控制器3将数据写入用户数据存储区域并测量写入速率，并且经由主机接口单元4将测量结果发送到存储器访问设备6。由此，存储器访问装置6能够识别写入速度。

10. 发明申请

US20080028129A1 Semiconductor Memory Device 有权
标题翻译：半导体存储器件
公开(公告)号：US20080028129A1
公开(公告)日：2008-01-31
申请号：US10598307
申请日：2005-02-25
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue
IPC分类号： G06F12/00
CPC分类号： G06F11/1441 , G06F11/1435
摘要： A writing completion flag table (105) for storing a writing completion flag corresponding to a predetermined storage unit such as a cluster or a physical block is stored in a non-volatile control memory (106). When completion of data writing into a predetermined storage unit is detected, a write completion flag is written in the corresponding address of the storage unit on the write completion flag table (105). Thus, it is possible to recognize that data has been written normally. Even when the flag indicating completion of writing into a page of the writing unit of the main storage memory cannot be written, it is possible to improve the writing reliability.
摘要翻译：用于存储与诸如集群或物理块的预定存储单元相对应的写入完成标志的写入完成标志表（105）被存储在非易失性控制存储器（106）中。当检测到写入预定存储单元的数据写入完成时，在写入完成标志表（105）上将写入完成标志写入存储单元的相应地址。因此，可以认识到数据已被正常写入。即使当指示写入主存储器的写入单元的页面的完成的标志不能被写入时，也可以提高写入可靠性。

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