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1. 发明授权

US08051268B2 Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method 失效
标题翻译：内存控制器，非易失性存储设备，非易失性存储系统和非易失性存储器地址管理方法
公开(公告)号：US08051268B2
公开(公告)日：2011-11-01
申请号：US11814202
申请日：2006-07-21
申请人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
发明人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7211
摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
摘要翻译：对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。逻辑地址范围分别与物理区域（段）相关联以管理地址。逻辑地址范围的大小相等。对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑地址范围和物理区域被分配。或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

2. 发明申请

US20090055618A1 MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD 失效
标题翻译：存储器控制器，非易失性存储设备，非易失性存储系统和非易失性存储器地址管理方法
公开(公告)号：US20090055618A1
公开(公告)日：2009-02-26
申请号：US11814202
申请日：2006-07-21
申请人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
发明人： Masahiro Nakanishi , Tetsushi Kasahara , Tomoaki Izumi , Kiminori Matsuno , Daisuke Kunimune , Kazuaki Tamura , Yoshiyuki Konishi
IPC分类号： G06F12/02 , G06F12/00 , G06F12/06
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7211
摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.
摘要翻译：对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。逻辑地址范围分别与物理区域（段）相关联以管理地址。逻辑地址范围的大小相等。对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑地址范围和物理区域被分配。或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

3. 发明授权

US08051270B2 Memory controller, nonvolatile storage device, nonvolatile storage system, and memory control method 有权
标题翻译：内存控制器，非易失性存储设备，非易失性存储系统和存储器控制方法
公开(公告)号：US08051270B2
公开(公告)日：2011-11-01
申请号：US11914989
申请日：2006-05-18
申请人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
发明人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A memory controller for reducing a time to create an address management table during initialization of a memory card. The memory controller includes a read-write memory for temporarily storing the address management table and a second memory controller for writing, in a nonvolatile memory, an address management table temporarily stored in the read-write memory. The second memory controller also writes address range specifying information that specifies an address range, when a data writing destination is changed from a first address range to a second address range. The memory controller includes an address management table generator for reading distributed management information used for managing a state of at least one physical block included in the destination address range specified by the address range specifying information during initialization, and to generate the address management table based on the distributed management information.
摘要翻译：一种用于在存储卡初始化期间减少创建地址管理表的时间的存储器控制器。存储器控制器包括用于临时存储地址管理表的读写存储器和用于在非易失性存储器中写入临时存储在读写存储器中的地址管理表的第二存储器控制器。当数据写入目的地从第一地址范围改变到第二地址范围时，第二存储器控制器还写入指定地址范围的地址范围指定信息。存储器控制器包括地址管理表发生器，用于读取用于管理初始化期间由地址范围指定信息指定的目的地地址范围中包括的至少一个物理块的状态的分布式管理信息，并且基于分布式管理信息。

4. 发明申请

US20080168252A1 Memory Controller, Nonvolatile Storage Device, Nonvolatile Storage System, and Memory Control Method 有权
标题翻译：存储控制器，非易失存储设备，非易失存储系统和存储器控制方法
公开(公告)号：US20080168252A1
公开(公告)日：2008-07-10
申请号：US11914989
申请日：2006-05-18
申请人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
发明人： Daisuke Kunimune , Masahiro Nakanishi , Manabu Inoue , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： The invention presents a memory controller capable of shortening the creation time of address management table at the time of initialization of memory card, while avoiding decline of access speed due to process of writing back the address management table in normal operation.The memory controller 114 includes a read-write memory 113 for temporarily storing the address management table 112, a memory control unit 122 for writing, in a nonvolatile memory 115, an address management table temporarily stored in the read-write memory and address range specifying information for specifying the changeover destination address range, when the physical block of data writing destination is changed over from a certain address range to other address range, and an address management table generation unit 107 for reading out the distributed management information used for managing the state of physical block included in the address range specified based on the address range specifying information at the time of initialization, and generating the address management table 112 based on the distributed management information being read out.
摘要翻译：本发明提出了一种能够缩短存储卡初始化时的地址管理表的创建时间的存储器控制器，同时避免由于在正常操作中写入地址管理表的过程而导致的访问速度的下降。存储器控制器114包括用于临时存储地址管理表112的读写存储器113，用于在非易失性存储器115中写入临时存储在读写存储器中的地址管理表和指定地址范围的存储器控制单元122 用于指定切换目的地地址范围的信息，当数据写入目的地的物理块从特定地址范围改变到其他地址范围时，以及地址管理表生成单元107，用于读出用于管理状态的分布式管理信息包括在基于初始化时的地址范围指定信息指定的地址范围内的物理块，并且基于被读出的分布式管理信息生成地址管理表112。

5. 发明申请

US20090019194A1 STORAGE DEVICE 有权
标题翻译：储存设备
公开(公告)号：US20090019194A1
公开(公告)日：2009-01-15
申请号：US11909749
申请日：2006-03-24
申请人： Masayuki Toyama , Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue
发明人： Masayuki Toyama , Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0676 , G06F11/1441
摘要： When a control unit (160) in a storage device (100) detects that a write end command or a data amount to be written has been transmitted from a host device (110), the control unit (160) saves control information required for writing data in a control information save memory (142). The control unit (160) also saves data which has not been written in storage medium into a buffer save memory (152) from a data buffer (151) and releases the busy state for the host device (110). The control unit (160) writes the saved data into a storage medium (120). Even if the power is turned OFF before completion of write, write can be performed into the storage medium (120) by using the saved data when the power is turned ON next time.
摘要翻译：当存储装置（100）中的控制单元（160）检测到从主机（110）发送写入结束命令或写入数据量时，控制单元（160）保存写入所需的控制信息控制信息中的数据保存存储器（142）。控制单元（160）还将从存储介质中未被写入的数据从数据缓冲器（151）保存到缓冲存储器（152）中，并且释放主机设备（110）的忙状态。控制单元（160）将保存的数据写入存储介质（120）。即使在完成写入之前电源被关闭，当下一次接通电源时，也可以通过使用保存的数据来对存储介质（120）进行写入。

6. 发明申请

US20070183179A1 Semiconductor memory card, access device and method 有权
标题翻译：半导体存储卡，接入设备和方法
公开(公告)号：US20070183179A1
公开(公告)日：2007-08-09
申请号：US10567241
申请日：2004-08-03
申请人： Takuji Maeda , Shinji Inoue , Yoshiho Gotoh , Jun Ohara , Masahiro Nakanishi , Shoichi Tsujita , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Koichi Horiuchi , Manabu Inoue , Makoto Ochi
发明人： Takuji Maeda , Shinji Inoue , Yoshiho Gotoh , Jun Ohara , Masahiro Nakanishi , Shoichi Tsujita , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Koichi Horiuchi , Manabu Inoue , Makoto Ochi
IPC分类号： G11C5/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0632 , G06F3/0679
摘要： A card information-storing portion is provided in a semiconductor memory card, and information relating to access performance such as access condition and access rate is held in the storing portion. Further, an access device acquires the held information from the semiconductor memory card to make it possible that the information can be used for control of a file system. This optimizes processing of the access device and the semiconductor memory card independent of differences in characteristics of semiconductor memory cards and management methods used, realizing high-rate access from the access device to a semiconductor memory card.
摘要翻译：在半导体存储卡中设置有卡片信息存储部分，并且存储与存取条件和访问速率有关的访问性能的信息被保存在存储部分中。此外，访问装置从半导体存储卡获取保持的信息，使得该信息可以用于文件系统的控制。这优化了访问设备和半导体存储卡的处理，而与半导体存储卡的特性差异以及使用的管理方法无关，实现了从访问设备到半导体存储卡的高速率访问。

7. 发明申请

US20060190670A1 Semiconductor memory device, controller, and read/write control method thereof 有权
标题翻译：半导体存储器件，控制器及其读/写控制方法
公开(公告)号：US20060190670A1
公开(公告)日：2006-08-24
申请号：US10553974
申请日：2004-10-13
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G06F12/06 , G06F2212/2022
摘要： A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.
摘要翻译：控制器102和四个闪速存储器F 0至F 3通过两个连接到两个存储器总线，并且每个闪速存储器被划分为大致相同大小的两个区域，以形成前半部分和后半个区域。在四存储器配置中，由主机设备指定的连续逻辑地址被划分为预定大小，并以按顺序重复循环的格式执行写入操作。。在双存储器配置中，写入操作以通过F 00，F 10，F 01，F 11重复循环的格式执行。因此，无论连接到控制器的闪存数量如何，控制器处理都是常见的。

8. 发明授权

US07818477B2 Storage device with buffer control unit 有权
标题翻译：带缓冲控制单元的存储设备
公开(公告)号：US07818477B2
公开(公告)日：2010-10-19
申请号：US11909749
申请日：2006-03-24
申请人： Masayuki Toyama , Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue
发明人： Masayuki Toyama , Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue
IPC分类号： G06F3/00 , G06F13/00 , G06F1/00 , G06F11/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0676 , G06F11/1441
摘要： When a control unit (160) in a storage device (100) detects that a write end command or a data amount to be written has been transmitted from a host device (110), the control unit (160) saves control information required for writing data in a control information save memory (142). The control unit (160) also saves data which has not been written in storage medium into a buffer save memory (152) from a data buffer (151) and releases the busy state for the host device (110). The control unit (160) writes the saved data into a storage medium (120). Even if the power is turned OFF before completion of write, write can be performed into the storage medium (120) by using the saved data when the power is turned ON next time.
摘要翻译：当存储装置（100）中的控制单元（160）检测到从主机（110）发送写入结束命令或写入数据量时，控制单元（160）保存写入所需的控制信息控制信息中的数据保存存储器（142）。控制单元（160）还将从存储介质中未被写入的数据从数据缓冲器（151）保存到缓冲存储器（152）中，并且释放主机设备（110）的忙状态。控制单元（160）将保存的数据写入存储介质（120）。即使在完成写入之前电源被关闭，当下一次接通电源时，也可以通过使用保存的数据来对存储介质（120）进行写入。

9. 发明申请

US20080307152A1 Memory Module, Memory Controller, Nonvolatile Storage, Nonvolatile Storage System, and Memory Read/Write Method 失效
标题翻译：内存模块，内存控制器，非易失性存储，非易失存储系统和内存读写方式
公开(公告)号：US20080307152A1
公开(公告)日：2008-12-11
申请号：US11817532
申请日：2006-03-01
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue , Masayuki Toyama , Kunihiro Maki
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno , Manabu Inoue , Masayuki Toyama , Kunihiro Maki
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , G06F11/1666 , G06F12/0246 , G06F2212/7201
摘要： In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.
摘要翻译：在具有破坏性读取类型的非易失性RAM的存储器中，归因于从非易失性RAM读取的数据的修复数量减少，并且存储器的总体寿命延长。在具有破坏性读取类型的非易失性RAM和易失性RAM的存储器中，并且在非易失性和易失性RAM中保持相同的数据，在读取时从易失性RAM中读出数据，并将数据写入易失性和非易失性RAM两者中。

10. 发明授权

US07203105B2 Semiconductor memory device, controller, and read/write control method thereof 有权
标题翻译：半导体存储器件，控制器及其读/写控制方法
公开(公告)号：US07203105B2
公开(公告)日：2007-04-10
申请号：US10553974
申请日：2004-10-13
申请人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
发明人： Masahiro Nakanishi , Tomoaki Izumi , Tetsushi Kasahara , Kazuaki Tamura , Kiminori Matsuno
IPC分类号： G11C7/00
CPC分类号： G06F12/06 , G06F2212/2022
摘要： A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.
摘要翻译：控制器102和四个闪速存储器F 0至F 3通过两个连接到两个存储器总线，并且每个闪速存储器被划分为大致相同大小的两个区域，以形成前半部分和后半个区域。在四存储器配置中，由主机设备指定的连续逻辑地址被划分为预定大小，并以按顺序重复循环的格式执行写入操作。。在双存储器配置中，写入操作以通过F 00，F 10，F 01，F 11重复循环的格式执行。因此，与控制器连接的闪存数量无关，控制器处理是常见的。

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