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    • 7. 发明授权
    • Semiconductor integrated circuit device with built-in timing regulator for output signals
    • 半导体集成电路器件具有内置定时调节器,用于输出信号
    • US06169435A
    • 2001-01-02
    • US09261742
    • 1999-03-03
    • Takaharu FujiiToshichika SakaiYasuo Yashiba
    • Takaharu FujiiToshichika SakaiYasuo Yashiba
    • H03H1126
    • H03L7/07G06F1/10H03K5/135
    • A semiconductor integrated circuit device is expected to output a multi-bit output signal at an extremely narrow timing in response to a system clock, wherein the semiconductor integrated circuit device includes synchronous latch circuits, a first phase-locked loop responsive to the system clock for producing a dummy data signal and a high-frequency intermediate clock signal, a delay circuit for producing a delayed clock signal delayed from the system clock by a predetermined number of clock pulses of the high-frequency intermediate clock signal and a second phase-locked loop comparing a dummy output signal with the delayed clock signal for producing a synchronous clock signal at appropriate timing, and the synchronous latch circuits is responsive to the synchronous clock signal for latching data signals and the dummy data signal, thereby outputting the output signals and the dummy output signal within the narrow timing.
    • 期望半导体集成电路器件响应于系统时钟以非常窄的定时输出多位输出信号,其中半导体集成电路器件包括同步锁存电路,响应于系统时钟的第一锁相环 产生伪数据信号和高频中间时钟信号;延迟电路,用于产生从系统时钟延迟预定数量的高频中间时钟信号的时钟脉冲的延迟时钟信号和第二锁相环 将虚拟输出信号与延迟的时钟信号进行比较,以在适当的定时产生同步时钟信号,并且同步锁存电路响应用于锁存数据信号和伪数据信号的同步时钟信号,从而输出输出信号和虚拟 输出信号在窄时间内。