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1. 发明授权

US06246274B1 Semiconductor device capable of trimming minimum delay time and maximum delay time of an output signal 失效
标题翻译：能够调整输出信号的最小延迟时间和最大延迟时间的半导体装置
公开(公告)号：US06246274B1
公开(公告)日：2001-06-12
申请号：US09267196
申请日：1999-03-12
申请人： Toshichika Sakai , Takaharu Fujii , Yasuo Yashiba
发明人： Toshichika Sakai , Takaharu Fujii , Yasuo Yashiba
IPC分类号： H03H1126
CPC分类号： H03K5/133
摘要： In a semiconductor device capable of obtaining an optimum delay time, a plurality of delay circuits are connected in series to one another through points of connections between two adjacent ones of the delay circuits to produce a plurality of reference delay signals derived from the delay circuits. One of the reference delay signals is decided as the optimum delay time with reference to a practical condition. Thus, the delay time can be varied in the semiconductor device.
摘要翻译：在能够获得最佳延迟时间的半导体器件中，多个延迟电路通过两个相邻延迟电路之间的连接点彼此串联连接，以产生从延迟电路导出的多个参考延迟信号。参考实际条件，将参考延迟信号中的一个决定为最佳延迟时间。因此，可以在半导体器件中改变延迟时间。

2. 发明授权

US06215345B1 Semiconductor device for setting delay time 失效
标题翻译：用于设置延迟时间的半导体器件
公开(公告)号：US06215345B1
公开(公告)日：2001-04-10
申请号：US09272577
申请日：1999-03-19
申请人： Yasuo Yashiba , Toshichika Sakai , Takaharu Fujii
发明人： Yasuo Yashiba , Toshichika Sakai , Takaharu Fujii
IPC分类号： H03K513
CPC分类号： G11C29/44 , G01R31/3016 , H03K5/14
摘要： The semiconductor device for setting a delay time, according to the present invention, comprises: a plurality of serially connected delay circuits into which a reference signal is input; a selector switch for selecting one of delay signals output from connection points between the delay circuits; and an internal selection signal generator for producing a selection signal for switching the selector switch to select one of the connection points.
摘要翻译：根据本发明的用于设置延迟时间的半导体器件包括：输入参考信号的多个串联的延迟电路; 选择开关，用于选择从所述延迟电路之间的连接点输出的延迟信号之一; 以及内部选择信号发生器，用于产生用于切换选择器开关以选择连接点之一的选择信号。

3. 发明授权

US06169435A Semiconductor integrated circuit device with built-in timing regulator for output signals 失效
标题翻译：半导体集成电路器件具有内置定时调节器，用于输出信号
公开(公告)号：US06169435A
公开(公告)日：2001-01-02
申请号：US09261742
申请日：1999-03-03
申请人： Takaharu Fujii , Toshichika Sakai , Yasuo Yashiba
发明人： Takaharu Fujii , Toshichika Sakai , Yasuo Yashiba
IPC分类号： H03H1126
CPC分类号： H03L7/07 , G06F1/10 , H03K5/135
摘要： A semiconductor integrated circuit device is expected to output a multi-bit output signal at an extremely narrow timing in response to a system clock, wherein the semiconductor integrated circuit device includes synchronous latch circuits, a first phase-locked loop responsive to the system clock for producing a dummy data signal and a high-frequency intermediate clock signal, a delay circuit for producing a delayed clock signal delayed from the system clock by a predetermined number of clock pulses of the high-frequency intermediate clock signal and a second phase-locked loop comparing a dummy output signal with the delayed clock signal for producing a synchronous clock signal at appropriate timing, and the synchronous latch circuits is responsive to the synchronous clock signal for latching data signals and the dummy data signal, thereby outputting the output signals and the dummy output signal within the narrow timing.
摘要翻译：期望半导体集成电路器件响应于系统时钟以非常窄的定时输出多位输出信号，其中半导体集成电路器件包括同步锁存电路，响应于系统时钟的第一锁相环产生伪数据信号和高频中间时钟信号;延迟电路，用于产生从系统时钟延迟预定数量的高频中间时钟信号的时钟脉冲的延迟时钟信号和第二锁相环将虚拟输出信号与延迟的时钟信号进行比较，以在适当的定时产生同步时钟信号，并且同步锁存电路响应用于锁存数据信号和伪数据信号的同步时钟信号，从而输出输出信号和虚拟输出信号在窄时间内。

4. 发明授权

US06131143A Multi-way associative storage type cache memory 失效
标题翻译：多路关联存储型缓存
公开(公告)号：US06131143A
公开(公告)日：2000-10-10
申请号：US089091
申请日：1998-06-02
申请人： Toshichika Sakai
发明人： Toshichika Sakai
IPC分类号： G06F15/78 , G06F12/08 , G11C15/04
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02B60/1225
摘要： An associative storage type cache memory is disclosed, which comprises a decoder for decoding an entry address designated by a data processing unit, a first tag memory for storing higher-order bits of an address tag, the first tag memory being common to multiple ways, second tag memories for storing lower-order bits of the address tag, the second tag memories corresponding to the individual ways, data memories for storing data designated by an address consisting of the contents of the first and second tag memories, a first comparator for comparing higher-order bits of a tag address with the contents of the first tag memory, second comparators for comparing lower-order bits of the tag address with the contents of the second tag memories, respectively, and a way selector for selecting data from the data memories corresponding to hit signals received from the first and second comparators and outputting the selected data.
摘要翻译：公开了一种关联存储型高速缓冲存储器，其包括用于对由数据处理单元指定的入口地址进行解码的解码器，用于存储地址标签的高位位置的第一标签存储器，第一标签存储器是多路通用的，用于存储地址标签的低阶位的第二标签存储器，对应于各路的第二标签存储器，用于存储由包括第一和第二标签存储器的内容的地址指定的数据的数据存储器，用于比较的第一比较器具有第一标签存储器的内容的标签地址的高阶比特，分别用于将标签地址的低位比特与第二标签存储器的内容进行比较的第二比较器，以及用于从数据中选择数据的路由选择器对应于从第一和第二比较器接收的命中信号的存储器并输出所选择的数据。

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