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1. 发明授权

US10340375B2 Epitaxial substrate for field effect transistor 有权
公开(公告)号：US10340375B2
公开(公告)日：2019-07-02
申请号：US12527142
申请日：2008-02-12
申请人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
发明人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
IPC分类号： H01L29/06 , H01L31/00 , H01L29/778 , H01L29/207 , H01L29/66 , H01L21/02 , H01L29/20
摘要： The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal includes the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.

2. 发明授权

US08350292B2 Gallium nitride epitaxial crystal, method for production thereof, and field effect transistor 有权
标题翻译：氮化镓外延晶体，其制造方法和场效应晶体管
公开(公告)号：US08350292B2
公开(公告)日：2013-01-08
申请号：US12527116
申请日：2008-02-07
申请人： Naohiro Nishikawa , Hiroyuki Sazawa , Masahiko Hata
发明人： Naohiro Nishikawa , Hiroyuki Sazawa , Masahiko Hata
IPC分类号： H01L29/66
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7783
摘要： The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer.
摘要翻译：本发明提供一种氮化镓型外延晶体，该晶体的制造方法以及使用该晶体的场效应晶体管。氮化镓型外延晶体包括基底和以下（a）至（e），其中包括氮化镓型晶体的连接层被布置在非氮化镓型绝缘层的开口中，以将第一缓冲层和p导电型半导体晶体层。（a）栅极层，（b）高纯度第一缓冲层，其含有与栅极层的基底侧上的界面接触的沟道层，（c）第二缓冲层，其设置在第一缓冲层的基底侧层，（d）配置在第二缓冲层的基板侧的非氮化镓系绝缘层，其一部分具有开口部，（e）配置在基板上的p导电型半导体晶体层绝缘层的衬底侧。

3. 发明授权

US07951685B2 Method for manufacturing semiconductor epitaxial crystal substrate 有权
标题翻译：半导体外延晶体基板的制造方法
公开(公告)号：US07951685B2
公开(公告)日：2011-05-31
申请号：US12310984
申请日：2007-09-14
申请人： Hiroyuki Sazawa , Naohiro Nishikawa , Masahiko Hata
发明人： Hiroyuki Sazawa , Naohiro Nishikawa , Masahiko Hata
IPC分类号： H01L21/76
CPC分类号： H01L29/66462 , H01L21/02458 , H01L21/0254 , H01L21/0257 , H01L21/0262 , H01L21/31608 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/517 , H01L29/518 , H01L29/78
摘要： The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.
摘要翻译：本发明提供一种具有电介质膜的氮化镓半导体外延晶体基板的制造方法，所述电介质膜具有低栅极泄漏电流和可忽略的低栅极滞后，漏极滞后和电流塌陷特性。半导体外延晶体基板的制造方法是制造半导体外延晶体基板的方法，其中，作为钝化膜或栅极绝缘体的非晶形式的氮化物电介质材料或氧化物电介质材料的介电层设置在通过金属有机化学气相沉积生长的氮化物半导体晶体层的表面。在该方法中，在外延生长室中生长氮化物半导体晶体层之后，在外延生长室中的氮化物半导体晶体层上生长电介质层。

4. 发明申请

US20110108885A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110108885A1
公开(公告)日：2011-05-12
申请号：US12933356
申请日：2009-03-18
申请人： Hiroyuki Sazawa , Naohiro Nishikawa , Yasuyuki Kurita , Masahiko Hata
发明人： Hiroyuki Sazawa , Naohiro Nishikawa , Yasuyuki Kurita , Masahiko Hata
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7787 , H01L29/1054 , H01L29/2003 , H01L29/42316 , H01L29/66522 , H01L29/78
摘要： The object of the present invention is to increase channel current density while a GaN-based field effect transistor operates in a normally-off mode. Provided is a semiconductor device comprising a group 3-5 compound semiconductor channel layer containing nitrogen, an electron supply layer that supplies electrons to the channel layer, a semiconductor layer that is formed on a side of the electron supply layer opposite the side facing the channel layer and that is an intrinsic or n-type group 3-5 compound semiconductor containing nitrogen, and a control electrode that is formed to contact the semiconductor layer or formed with an intermediate layer interposed between itself and the semiconductor layer.
摘要翻译：本发明的目的是增加沟道电流密度，而GaN系场效应晶体管以常关状态工作。提供了一种半导体器件，其包括含有氮的组3-5化合物半导体沟道层，向沟道层提供电子的电子供给层，形成在电子供给层的与沟道侧相对的一侧上的半导体层并且是含有氮的固有或n型组3-5化合物半导体，以及形成为与半导体层接触或形成有介于其自身与半导体层之间的中间层的控制电极。

5. 发明申请

US20100019277A1 EPITAXIAL SUBSTRATE FOR FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：场效应晶体管的外延衬底
公开(公告)号：US20100019277A1
公开(公告)日：2010-01-28
申请号：US12527142
申请日：2008-02-12
申请人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
发明人： Masahiko Hata , Hiroyuki Sazawa , Naohiro Nishikawa
IPC分类号： H01L29/20
CPC分类号： H01L29/7783 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02581 , H01L21/0262 , H01L29/2003 , H01L29/207 , H01L29/66462
摘要： The present invention provides an epitaxial substrate for field effect transistor. In the epitaxial substrate for field effect transistor, a nitride-based Group III-V semiconductor epitaxial crystal containing Ga is interposed between the ground layer and the operating layer, and the nitride-based Group III-V semiconductor epitaxial crystal comprises the following (i), (ii) and (iii). (i) a first buffer layer containing Ga or Al and containing a high resistivity crystal layer having added thereto compensation impurity element present in the same period as Ga in the periodic table and having small atomic number; (ii) a second buffer layer containing Ga or Al, laminated on the operating layer side of the first buffer layer; and (iii) a high purity epitaxial crystal layer containing acceptor impurities in a slight amount such that non-addition or depletion state can be maintained, provided between the high resistivity layer and the operating layer.
摘要翻译：本发明提供一种用于场效晶体管的外延衬底。在场效晶体管的外延衬底中，在接地层和工作层之间插入含有Ga的基于氮化物的III-V族III族半导体外延晶体，氮化物系III-V族半导体外延晶体包括以下（i ），（ii）和（iii）。（i）包含Ga或Al的第一缓冲层，并且含有添加了与周期表中与Ga相同的周期中具有小原子序数的补偿杂质元素的高电阻率晶体层; （ii）层叠在第一缓冲层的工作层侧的含有Ga或Al的第二缓冲层; 和（iii）在高电阻率层和操作层之间提供含有少量的受主杂质的高纯度外延晶体层，使得能够维持非添加或耗尽状态。

6. 发明申请

US20110042719A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110042719A1
公开(公告)日：2011-02-24
申请号：US12933340
申请日：2009-03-18
申请人： Hiroyuki Sazawa , Naohiro Nishikawa , Yasuyukl Kurita , Masahiko Hata
发明人： Hiroyuki Sazawa , Naohiro Nishikawa , Yasuyukl Kurita , Masahiko Hata
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/1066 , H01L29/2003 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L2924/0002 , H01L2924/00
摘要： It is an objective of the present invention to increase channel current density while allowing a GaN field effect transistor to perform normally-off operation.Provided is a a semiconductor device comprising a group 3-5 compound semiconductor channel layer including nitrogen; an electron supply layer that has a groove in a surface thereof that is opposite a surface facing the channel layer and that supplies the channel layer with electrons; a p-type semiconductor layer that is formed in the groove of the electron supply layer; and a control electrode formed directly on the p-type semiconductor layer or on an intermediate layer formed on the p-type semiconductor layer.
摘要翻译：本发明的目的是增加沟道电流密度，同时允许GaN场效应晶体管执行常关操作。提供一种半导体器件，其包括含有氮的组3-5化合物半导体沟道层; 电子供给层，其表面中具有与面向沟道层的表面相对的沟槽，并且向沟道层提供电子; 形成在电子供给层的槽内的p型半导体层; 以及直接形成在p型半导体层上或形成在p型半导体层上的中间层上的控制电极。

7. 发明申请

US20100117094A1 GALLIUM NITRIDE EPITAXIAL CRYSTAL, METHOD FOR PRODUCTION THEREOF, AND FIELD EFFECT TRANSISTOR 有权
标题翻译：氮化铝外延晶体，其生产方法和场效应晶体管
公开(公告)号：US20100117094A1
公开(公告)日：2010-05-13
申请号：US12527116
申请日：2008-02-07
申请人： Naohiro Nishikawa , Hiroyuki Sazawa , Masahiko Hata
发明人： Naohiro Nishikawa , Hiroyuki Sazawa , Masahiko Hata
IPC分类号： H01L29/772 , H01L29/205 , H01L21/20
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7783
摘要： The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer.
摘要翻译：本发明提供一种氮化镓型外延晶体，该晶体的制造方法以及使用该晶体的场效应晶体管。氮化镓型外延晶体包括基底和以下（a）至（e），其中包括氮化镓型晶体的连接层被布置在非氮化镓型绝缘层的开口中，以将第一缓冲层和p导电型半导体晶体层。（a）栅极层，（b）高纯度第一缓冲层，其含有与栅极层的基底侧上的界面接触的沟道层，（c）第二缓冲层，其设置在第一缓冲层的基底侧层，（d）配置在第二缓冲层的基板侧的非氮化镓系绝缘层，其一部分具有开口部，（e）配置在基板上的p导电型半导体晶体层绝缘层的衬底侧。

8. 发明申请

US20100084742A1 Method for manufacturing semiconductor epitaxial crystal substrate 有权
标题翻译：半导体外延晶体基板的制造方法
公开(公告)号：US20100084742A1
公开(公告)日：2010-04-08
申请号：US12310984
申请日：2007-09-14
申请人： Hiroyuki Sazawa , Naohiro Nishikawa , Masahiko Hata
发明人： Hiroyuki Sazawa , Naohiro Nishikawa , Masahiko Hata
IPC分类号： H01L29/20 , H01L21/20 , H01L21/31 , H01L29/423
CPC分类号： H01L29/66462 , H01L21/02458 , H01L21/0254 , H01L21/0257 , H01L21/0262 , H01L21/31608 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/517 , H01L29/518 , H01L29/78
摘要： The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.
摘要翻译：本发明提供一种具有电介质膜的氮化镓半导体外延晶体基板的制造方法，所述电介质膜具有低栅极泄漏电流和可忽略的低栅极滞后，漏极滞后和电流塌陷特性。半导体外延晶体基板的制造方法是制造半导体外延晶体基板的方法，其中，作为钝化膜或栅极绝缘体的非晶形式的氮化物电介质材料或氧化物电介质材料的介电层设置在通过金属有机化学气相沉积生长的氮化物半导体晶体层的表面。在该方法中，在外延生长室中生长氮化物半导体晶体层之后，在外延生长室中的氮化物半导体晶体层上生长电介质层。

9. 发明授权

US08053811B2 Group 3-5 nitride semiconductor multilayer substrate, method for manufacturing group 3-5 nitride semiconductor free-standing subtrate, and semiconductor element 失效
标题翻译： 3-5族氮化物半导体多层基板，第3-5族氮化物半导体独立减渣剂的制造方法以及半导体元件
公开(公告)号：US08053811B2
公开(公告)日：2011-11-08
申请号：US11920563
申请日：2006-05-02
申请人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
发明人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
IPC分类号： H01L21/00
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01S2304/12
摘要： A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (12). Then, after forming a group 3-5 nitride semiconductor crystalline layer (14) by selective growing, the group 3-5 nitride semiconductor crystalline layer (14) and the base substrate (11) are separated. The crystallinity of the semiconductor layer (12) is lower than that of the group 3-5 nitride semiconductor crystalline layer (14).
摘要翻译：提供3-5族氮化物半导体多层基板（1）及其制造方法。半导体层（12）形成在基底（11）上，在半导体层（12）上形成掩模（13）。然后，通过选择性生长形成3-5族氮化物半导体结晶层（14）后，分离3-5族氮化物半导体结晶层（14）和基底基板（11）。半导体层（12）的结晶度低于3-5族氮化物半导体晶体层（14）的结晶度。

10. 发明申请

US20110119674A1 SCHEDULING METHOD, SCHEDULING APPARATUS AND MULTIPROCESSOR SYSTEM 有权
标题翻译：调度方法，调度装置和多处理器系统
公开(公告)号：US20110119674A1
公开(公告)日：2011-05-19
申请号：US13012054
申请日：2011-01-24
申请人： Naohiro Nishikawa
发明人： Naohiro Nishikawa
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A thread status managing unit organizes a plurality of threads into groups and manages the status of the thread groups. A ready queue queues thread groups in a ready state or a running state in the order of priority and, within the same priority level, in the FIFO order. An assignment list generating unit sequentially retrieves the thread groups from the ready queue. The assignment list appends a retrieved thread group to a thread assignment list only when all threads belonging to the retrieved thread group are assignable to the respective processors at the same time. A thread assigning unit assigns all threads belonging to the thread groups stored in the thread assignment list to the respective processors.
摘要翻译：线程状态管理单元将多个线程组织成组并管理线程组的状态。准备好的队列将处于就绪状态或运行状态的线程组以优先级顺序排队，并且在同一优先级别内以FIFO顺序排队。分配表生成单元从就绪队列顺序地检索线程组。只有当属于检索到的线程组的所有线程可以同时分配给相应的处理器时，分配列表将检索到的线程组添加到线程分配列表。线程分配单元将属于线程分配列表中存储的线程组的所有线程分配给各个处理器。

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