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1. 发明申请

US20090085165A1 Group 3-5 Nitride Semiconductor Multilayer Substrate, Method for Manufacturing Group 3-5 Nitride Semiconductor Free-Standing Subtrate, and Semiconductor Element 失效
标题翻译：第3-5族氮化物半导体多层基板，制造方法3-5氮化硅半导体自由放电，半导体元件
公开(公告)号：US20090085165A1
公开(公告)日：2009-04-02
申请号：US11920563
申请日：2006-05-02
申请人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
发明人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
IPC分类号： H01L21/20 , H01L29/20
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01S2304/12
摘要： A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (12). Then, after forming a group 3-5 nitride semiconductor crystalline layer (14) by selective growing, the group 3-5 nitride semiconductor crystalline layer (14) and the base substrate (11) are separated. The crystallinity of the semiconductor layer (12) is lower than that of the group 3-5 nitride semiconductor crystalline layer (14).
摘要翻译：提供3-5族氮化物半导体多层基板（1）及其制造方法。半导体层（12）形成在基底（11）上，在半导体层（12）上形成掩模（13）。然后，通过选择性生长形成3-5族氮化物半导体结晶层（14）后，分离3-5族氮化物半导体结晶层（14）和基底基板（11）。半导体层（12）的结晶度低于3-5族氮化物半导体晶体层（14）的结晶度。

2. 发明授权

US08053811B2 Group 3-5 nitride semiconductor multilayer substrate, method for manufacturing group 3-5 nitride semiconductor free-standing subtrate, and semiconductor element 失效
标题翻译： 3-5族氮化物半导体多层基板，第3-5族氮化物半导体独立减渣剂的制造方法以及半导体元件
公开(公告)号：US08053811B2
公开(公告)日：2011-11-08
申请号：US11920563
申请日：2006-05-02
申请人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
发明人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
IPC分类号： H01L21/00
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01S2304/12
摘要： A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (12). Then, after forming a group 3-5 nitride semiconductor crystalline layer (14) by selective growing, the group 3-5 nitride semiconductor crystalline layer (14) and the base substrate (11) are separated. The crystallinity of the semiconductor layer (12) is lower than that of the group 3-5 nitride semiconductor crystalline layer (14).
摘要翻译：提供3-5族氮化物半导体多层基板（1）及其制造方法。半导体层（12）形成在基底（11）上，在半导体层（12）上形成掩模（13）。然后，通过选择性生长形成3-5族氮化物半导体结晶层（14）后，分离3-5族氮化物半导体结晶层（14）和基底基板（11）。半导体层（12）的结晶度低于3-5族氮化物半导体晶体层（14）的结晶度。

3. 发明申请

US20060172512A1 Substrate of gallium nitride single crystal and process for producing the same 有权
标题翻译：氮化镓单晶衬底及其制造方法
公开(公告)号：US20060172512A1
公开(公告)日：2006-08-03
申请号：US10546983
申请日：2004-03-04
申请人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yoshinobu Ono
发明人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yoshinobu Ono
IPC分类号： H01L21/20
CPC分类号： H01L21/02389 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01L21/02647
摘要： The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0≦x≦1, 0≦y≦1, 0≦z≦1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.
摘要翻译：本发明涉及一种用于制造具有由通式为III-V族化合物半导体晶体表示的外延基板的方法，该III-V族化合物半导体晶体由以下通式表示：＆lt; N（其中，x + y + z = 1,0 <= x <=1,0,0≤i≤1,0<= z <= 1）具有降低的位错密度，包括第一步覆盖具有由与III-V族化合物半导体不同的材料制成的掩模，使得通过使用具有多个投影形状的III-V族化合物半导体晶体，仅使晶体周围的部分构成开口，第二步是使 III-V族化合物半导体晶体通过在开口处使用III-V族化合物半导体晶体作为晶种横向。根据本发明，获得具有位错密度低且翘曲少的III-V族化合物半导体晶体的外延基板。

4. 发明授权

US07399687B2 Substrate of gallium nitride single crystal and process for producing the same 有权
标题翻译：氮化镓单晶衬底及其制造方法
公开(公告)号：US07399687B2
公开(公告)日：2008-07-15
申请号：US10546983
申请日：2004-03-04
申请人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yoshinobu Ono
发明人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yoshinobu Ono
IPC分类号： H01L21/20
CPC分类号： H01L21/02389 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01L21/02647
摘要： The present invention relates to a method for producing an epitaxial substrate having a III-V group compound semiconductor crystal represented by the general formula InxGayAlzN (wherein, x+y+z=1, 0≦x≦1, 0≦y≦1, 0≦z≦1) having reduced dislocation density, comprising a first step of covering with a mask made of a different material from the III-V group compound semiconductor so that only portions around points of the crystal constitute openings by using a III-V group compound semiconductor crystal having a plurality of projection shapes and a second step of growing the III-V group compound semiconductor crystal laterally by using the III-V group compound semiconductor crystal at the opening as a seed crystal. According to the present invention, an epitaxial substrate having a III-V group compound semiconductor crystal having low dislocation density and little warp is obtained.
摘要翻译：本发明涉及一种用于制造具有由通式为III-V族化合物半导体晶体表示的外延基板的方法，该III-V族化合物半导体晶体由以下通式表示：＆lt; N（其中，x + y + z = 1,0 <= x <=1,0,0≤i≤1,0<= z <= 1）具有降低的位错密度，包括第一步覆盖具有由与III-V族化合物半导体不同的材料制成的掩模，使得通过使用具有多个投影形状的III-V族化合物半导体晶体，仅使晶体周围的部分构成开口，第二步是使 III-V族化合物半导体晶体通过在开口处使用III-V族化合物半导体晶体作为晶种横向。根据本发明，获得具有位错密度低且翘曲少的III-V族化合物半导体晶体的外延基板。

5. 发明授权

US06503610B2 Group III-V compound semiconductor and method of producing the same 有权
标题翻译： III-V族化合物半导体及其制造方法
公开(公告)号：US06503610B2
公开(公告)日：2003-01-07
申请号：US09814875
申请日：2001-03-23
申请人： Kazumasa Hiramatsu , Hideto Miyake , Takayoshi Maeda , Yasushi Iyechika
发明人： Kazumasa Hiramatsu , Hideto Miyake , Takayoshi Maeda , Yasushi Iyechika
IPC分类号： C30B100
CPC分类号： C30B23/02 , C30B25/02 , C30B29/403 , C30B29/406 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L33/0066 , H01L33/007 , H01S2304/12 , Y10T428/24926
摘要： Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
摘要翻译：提供了一种在不增加再生长层的厚度的情况下生产具有低位错密度的III-V族化合物半导体的方法，该方法包括使用掩模图案的再生长过程，以及再生长中的穿孔位错层被图案上形成的空隙终止。

6. 发明授权

US06844574B1 III-V compound semiconductor 失效
标题翻译： III-V族化合物半导体
公开(公告)号：US06844574B1
公开(公告)日：2005-01-18
申请号：US09522707
申请日：2000-03-10
申请人： Kazumasa Hiramatsu , Hideto Miyake , Takayoshi Maeda , Yasushi Iyechika
发明人： Kazumasa Hiramatsu , Hideto Miyake , Takayoshi Maeda , Yasushi Iyechika
IPC分类号： H01L21/205 , H01L33/00 , H01L33/02 , H01S5/323 , H01L29/04
CPC分类号： H01L33/025 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01L21/02647 , H01L33/0075 , H01S5/32341
摘要： Provided is a III-V compound semiconductor having a layer formed from a first III-V compound semiconductor expressed by the general formula InuGavAlwN (where 0≦u≦1, 0≦v≦1, 0≦w≦1, u+v+w=1), a pattern formed on the layer from a material different not only from the first III-V compound semiconductor but also from a second III-V compound semiconductor hereinafter described, and a layer formed on the first III-V compound semiconductor and the pattern from the second III-V compound semiconductor expressed by the general formula InxGayAlzN (where 0≦x≦1, 0≦y≦1, 0≦x≦1, x+y+z=1), wherein the full width at half maximum of the (0004) reflection X-ray rocking curve of the second III-V compound semiconductor is 700 seconds or less regardless of the direction of X-ray incidence. In the III-V compound semiconductor, which is a high quality semiconductor, the occurrence of low angle grain boundaries is suppressed.
摘要翻译：提供了具有由通式InuGavAlwN表示的第一III-V族化合物半导体形成的层的III-V族化合物半导体（其中0≤u≤1,0<=v≤1,0<= w < 1，u + v + w = 1），从不同于第一III-V族化合物半导体的材料形成在该层上的图案，以及由下文所述的第二III-V族化合物半导体形成的层第一III-V族化合物半导体和由通式InxGayAlzN表示的第二III-V族化合物半导体的图案（其中0 <= x <= 1,0 <= y <=1,0,0≤x≤1，x + y + z = 1），其中，与X射线入射方向无关地，第二III-V族化合物半导体的（0004）反射X射线摇摆曲线的半峰全宽为700秒以下。在作为高质量半导体的III-V族化合物半导体中，抑制了低角度晶界的发生。

7. 发明授权

US06756246B2 Method for fabricating III-V group compound semiconductor 失效
标题翻译：制备III-V族化合物半导体的方法
公开(公告)号：US06756246B2
公开(公告)日：2004-06-29
申请号：US10105238
申请日：2002-03-26
申请人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yasushi Iyechika
发明人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yasushi Iyechika
IPC分类号： H01L21302
CPC分类号： C30B25/02 , C30B29/403 , C30B29/406 , H01L21/02389 , H01L21/0242 , H01L21/02447 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647
摘要： A method for fabricating a GaN-based III-V Group compound semiconductor is provided that utilizes a regrowth method based on the HVPE method to form a second III-V Group compound semiconductor layer having a flat surface on a first III-V Group compound semiconductor layer formed with a mask layer. The method uses a mixed carrier gas of hydrogen gas and nitrogen gas to control formation of a facet group including at least the {33-62} facet by the regrowth, and conducting the regrowth until a plane parallel to the surface of the first III-V Group compound semiconductor layer is once annihilated, thereby fabricating a III-V Group compound semiconductor having low dislocation density.
摘要翻译：提供一种用于制造GaN基III-V族化合物半导体的方法，其利用基于HVPE方法的再生方法在第一III-V族化合物半导体上形成具有平坦表面的第二III-V族化合物半导体层层形成有掩模层。该方法使用氢气和氮气的混合载气来控制由再生长至少包括{33-62}面的小面的形成，并进行再生长，直到平行于第一III- V族化合物半导体层一旦被消除，从而制造具有低位错密度的III-V族化合物半导体。

8. 发明授权

US06946308B2 Method of manufacturing III-V group compound semiconductor 失效
标题翻译：制备III-V族化合物半导体的方法
公开(公告)号：US06946308B2
公开(公告)日：2005-09-20
申请号：US10396565
申请日：2003-03-26
申请人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yasushi Iyechika
发明人： Kazumasa Hiramatsu , Hideto Miyake , Shinya Bohyama , Takayoshi Maeda , Yasushi Iyechika
IPC分类号： C30B29/38 , C30B25/02 , H01L21/205 , H01L29/201 , H01L33/32 , H01L21/00 , H01L33/00
CPC分类号： C30B25/02 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0242 , H01L21/02447 , H01L21/02458 , H01L21/0254 , H01L21/0262
摘要： When a crystal layer of III-V Group nitride compound semiconductor is formed, a nitride compound semiconductor layer is first overlaid on a substrate to form a base layer and a III-V Group nitride compound semiconductor represented by the general formula InxGayAlzN (where 0≦x≦1, 0≦y≦1, 0≦z≦1, x+y+z=1) is epitaxially grown on the base layer by hydride vapor phase epitaxy at a deposition pressure of not lower than 800 Torr. By making the deposition pressure not lower than 800 Torr, the crystallinity of the III-V Group nitride compound semiconductor can be markedly improved and its defect density reduced.
摘要翻译：当形成III-V族氮化物化合物半导体的晶体层时，首先将氮化物化合物半导体层重叠在基板上以形成基底层，并且由通式In x x表示的III-V族氮化物化合物半导体（其中0≤x≤1,0<= y <=1,0,0≤z≤1，x + y + z = 1）在不低于800托的沉积压力下通过氢化物气相外延在基底层上外延生长。通过使沉积压力不低于800托，III-V族氮化物化合物半导体的结晶度可以显着提高，并且其缺陷密度降低。

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