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1. 发明授权

US5870289A Chip connection structure having diret through-hole connections through adhesive film and wiring substrate 失效
标题翻译：芯片连接结构具有通过粘合膜和布线基板的直通通孔连接
公开(公告)号：US5870289A
公开(公告)日：1999-02-09
申请号：US572747
申请日：1995-12-14
申请人： Masahide Tokuda , Takeshi Kato , Hiroyuki Itoh , Masayoshi Yagyu , Yuuji Fujita , Mitsuo Usami
发明人： Masahide Tokuda , Takeshi Kato , Hiroyuki Itoh , Masayoshi Yagyu , Yuuji Fujita , Mitsuo Usami
IPC分类号： H01L21/60 , H01L21/68 , H01L21/98 , H01L23/12 , H01L23/28 , H01L23/29 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L25/18 , H05K1/11 , H05K1/18 , H05K3/30 , H05K3/32 , H05K3/40 , H05K1/14 , H05K1/16 , H05K7/02 , H05K7/06
CPC分类号： H01L21/6836 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68354 , H01L2224/0401 , H01L2224/04105 , H01L2224/16 , H01L2224/16235 , H01L2224/20 , H01L2224/24227 , H01L2224/451 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4518 , H01L2224/45184 , H01L2224/48091 , H01L2224/48227 , H01L2224/83192 , H01L2224/9202 , H01L2224/92144 , H01L2224/97 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/351 , H05K1/112 , H05K3/303 , H05K3/4007
摘要： A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.
摘要翻译：用于将集成电路芯片连接到实现高密度封装，高密度连接，高速信号传输和低成本的布线基板的结构。集成电路通过使用粘合膜的倒装芯片贴片连接到布线基板。直接通孔连接形成在连接焊盘的正下方，以穿过粘合膜和布线基板。这种直接通孔连接将连接垫直接连接到电线。由于芯片的面积和厚度减小，芯片以高密度安装，高密度输入和输出通过微小的二维连接来实现。直接连接到芯片的短线连接允许高速信号传输，并且通过应力分散来确保高可靠性。低成本的包装可以通过简单的工艺和设施来实现。

2. 发明授权

US4868420A Flip-flop circuit 失效
标题翻译：触发电路
公开(公告)号：US4868420A
公开(公告)日：1989-09-19
申请号：US273729
申请日：1988-11-18
申请人： Hiroyuki Itoh , Masayoshi Yagyu , Toshio Yamada , Masaru Osanai , Akira Masaki , Mitsuo Usami , Tohru Kobayashi , Masato Hamamoto
发明人： Hiroyuki Itoh , Masayoshi Yagyu , Toshio Yamada , Masaru Osanai , Akira Masaki , Mitsuo Usami , Tohru Kobayashi , Masato Hamamoto
IPC分类号： H03K3/037 , H03K3/2885
CPC分类号： H03K3/2885 , H03K3/0375
摘要： An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.
摘要翻译：提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。

3. 发明授权

US5184027A Clock signal supply system 失效
标题翻译：时钟信号供电系统
公开(公告)号：US5184027A
公开(公告)日：1993-02-02
申请号：US688696
申请日：1991-04-22
申请人： Noboru Masuda , Ryotaro Kamikawai , Masayoshi Yagyu , Masakazu Yamamoto , Hiroyuki Itoh , Tatsuya Saito
发明人： Noboru Masuda , Ryotaro Kamikawai , Masayoshi Yagyu , Masakazu Yamamoto , Hiroyuki Itoh , Tatsuya Saito
IPC分类号： C04B35/45 , G06F1/10 , H01L39/12 , H01L39/24
CPC分类号： C04B35/4504 , G06F1/10 , H01L39/126 , H01L39/2419
摘要： A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.
摘要翻译：时钟信号供应系统提供时钟信号的自动精确相位调整。该系统包括产生时钟信号的振荡器和产生相对于由振荡器产生的时钟信号具有预定关系的参考信号的参考发生器。在要接收时钟信号的每个位置，提供调整电路以调整所接收的时钟信号的相位。这种调整电路可以包括可变延迟电路，其接收时钟信号并且产生由具有变化的延迟的时钟信号构成的输出到连接电路的其余部分。此外，可变延迟的输出被反馈到相位差检测电路。参考信号是相位差检测电路的第二输入。该相位差检测电路比较参考信号和可变延迟电路的输出的差异，并将该控制信号产生到可变延迟电路，该可变延迟电路将进一步调节所接收的时钟信号的相位。该调整是在要接收时钟信号的每个位置处执行的，从而提供对时钟信号的相位的自动调整。

4. 发明授权

US06191647B1 Low noise integrated circuit device for reducing a noise on LSI power supply nets to supply electric charges required to operate IC 有权
标题翻译：低噪声集成电路器件，用于降低LSI电源网络上的噪声，以提供操作IC所需的电荷
公开(公告)号：US06191647B1
公开(公告)日：2001-02-20
申请号：US09220372
申请日：1998-12-24
申请人： Katsuya Tanaka , Masayoshi Yagyu , Tatsuya Saito , Tetsuya Uemura , Tomohisa Iwanaga , Hiroki Yamashita , Takeshi Kato
发明人： Katsuya Tanaka , Masayoshi Yagyu , Tatsuya Saito , Tetsuya Uemura , Tomohisa Iwanaga , Hiroki Yamashita , Takeshi Kato
IPC分类号： H03K500
CPC分类号： H03K19/00346
摘要： A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.
摘要翻译：需要具有巨大面积的电容器来减小集成电路的LSI电源网（-DELTAVDD）上的噪声，因为旁路电容器只能使用一部分累积的电荷。基于降低放电高电压的电容器的噪声降低电路，对LSI电源网（-DELTAVDD）的噪声产生相反极性（+ DELTAVDD）的噪声来抑制LSI电源网的噪声。即使使用容量小的冷凝器，也能够获得与大容量的旁路电容器相当的噪声降低效果。

5. 发明申请

US20070184687A1 Circuit board provided with digging depth detection structure and transmission device with the same mounted 审中-公开
标题翻译：电路板配有挖掘深度检测结构和传输装置相同的安装
公开(公告)号：US20070184687A1
公开(公告)日：2007-08-09
申请号：US11657462
申请日：2007-01-25
申请人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
发明人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
IPC分类号： H05K1/00
CPC分类号： H05K1/0268 , H05K1/0237 , H05K3/0047 , H05K3/429 , H05K2203/0207 , H05K2203/0242 , H05K2203/163 , H05K2203/175
摘要： One of a group which is located on the side of a main surface of the circuit board than the one conductive layer of the plurality of conductive layers is used as a terminal to detect the digging depth of the through hole, and the digging of the through hole is stopped according to the change of the conductive state between the detection terminal and the through hole (or the one conductive layer which is electrically connected to this). A circuit board is formed so that the detection terminal in a group of the plurality of conductive layers contacts with the drill which dig the through hole and a group of the conductive layers except the detection terminal does not contact with the drill, respectively.
摘要翻译：使用位于电路板的主表面侧的多个导电层的一个导电层中的一个作为端子来检测通孔的挖掘深度，并且挖掘通孔根据检测端子和通孔（或与其电连接的一个导电层）之间的导电状态的变化来停止孔。形成电路板，使得多个导电层中的一组中的检测端子与钻孔相接触，钻头分别钻出通孔，除了检测端子之外的一组导电层不与钻头接触。

6. 发明授权

US5604840A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5604840A
公开(公告)日：1997-02-18
申请号：US38839
申请日：1993-03-29
申请人： Mitsuo Asai , Noboru Masuda , Moritoshi Yasunaga , Masayoshi Yagyu , Minoru Yamada , Katsunari Shibata
发明人： Mitsuo Asai , Noboru Masuda , Moritoshi Yasunaga , Masayoshi Yagyu , Minoru Yamada , Katsunari Shibata
IPC分类号： G06N3/04 , G06N3/063 , G06F15/18
CPC分类号： G06N3/063 , G06N3/0454
摘要： An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.
摘要翻译：信息处理装置由输入层，隐藏层和输出层构成，并且以神经元模型进行计算。在信息处理装置中，包括输入层，隐藏层和输出层的正向网络对外部输入数据执行计算，以确定其输出值，并且包括输出层和隐藏层的反向网络执行计算对于给定输入预期的输出值来确定学习信号值。信息处理装置传送前向网络和后向网络之间的输出值和学习值，以修改神经元模型的突触权重。

7. 发明授权

US5165010A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US5165010A
公开(公告)日：1992-11-17
申请号：US461080
申请日：1990-01-04
申请人： Noboru Masuda , Moritoshi Yasunaga , Minoru Yamada , Akira Masaki , Mitsuo Asai , Yuzo Hirai , Masayoshi Yagyu , Takehisa Hayashi , Toshio Doi , Kenichi Ishibashi
发明人： Noboru Masuda , Moritoshi Yasunaga , Minoru Yamada , Akira Masaki , Mitsuo Asai , Yuzo Hirai , Masayoshi Yagyu , Takehisa Hayashi , Toshio Doi , Kenichi Ishibashi
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06N3/04
摘要： An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

8. 发明授权

US07965765B2 Adjustment method, circuit, receiver circuit and transmission equipment of waveform equalization coefficient 有权
标题翻译：调整方法，电路，接收机电路和传输设备的波形均衡系数
公开(公告)号：US07965765B2
公开(公告)日：2011-06-21
申请号：US11965783
申请日：2007-12-28
申请人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
发明人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.
摘要翻译：在波形均衡系数的调整方法中，仅在任意信号序列的情况下测量抖动和幅度之一并且调整波形均衡系数。特别地，使用除010信号或101信号之外的接收信号的信号，测量码反转时间。由于在使用这种信号的情况下的代码反转时间与传统技术相比变得更陡峭，所以可以减小波形均衡系数的调整时间。

9. 发明授权

US07795944B2 Low-offset input circuit including amplifier circuit to correct circuit characteristics to cancel offset of the input circuit 失效
标题翻译：低失调输入电路包括放大器电路，用于校正电路特性以消除输入电路的偏移
公开(公告)号：US07795944B2
公开(公告)日：2010-09-14
申请号：US12183080
申请日：2008-07-31
申请人： Masayoshi Yagyu , Hiroki Yamashita , Takashi Takemoto
发明人： Masayoshi Yagyu , Hiroki Yamashita , Takashi Takemoto
IPC分类号： H03L5/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45744 , H03F3/45968 , H03F2203/45212 , H03F2203/45702
摘要： In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit. In a signal receiver circuit having an input circuit, an automatic zero amplifier, an analog/digital converter circuit, an encoder circuit, and a signal holding circuit, an output error signal of the input circuit is amplified by the automatic zero amplifier, and the signal is digitalized or the digitalized signal is encoded as the occasion demands, and held by the holding circuit, and the circuit characteristic variation of the input circuit is adjusted by the held signal.
摘要翻译：在输入电路对信号接收操作的电路特性变化的影响不能忽略的信号传输系统中，提供了一种实现低偏移输入电路的方法，该低失调输入电路能够进行高速操作并且总是继续信号接收操作而不增加半导体集成电路的端子数量，而不需要向半导体集成电路的外部提供额外的信号观测装置和变化调整量计算装置。在具有输入电路，自动零放大器，模拟/数字转换器电路，编码器电路和信号保持电路的信号接收器电路中，输入电路的输出误差信号由自动零放大器放大，信号被数字化或数字化信号根据场合需要编码并由保持电路保持，并且通过保持信号调整输入电路的电路特性变化。

10. 发明授权

US07319575B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07319575B2
公开(公告)日：2008-01-15
申请号：US11288323
申请日：2005-11-29
申请人： Tatsuya Kawashimo , Hiroki Yamashita , Masayoshi Yagyu
发明人： Tatsuya Kawashimo , Hiroki Yamashita , Masayoshi Yagyu
IPC分类号： H02H9/00 , H03K17/16
CPC分类号： H03F1/52 , H01L27/0266
摘要： This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.
摘要翻译：本发明提供一种半导体器件，其中可以以小的裸片面积实现ESD保护电路和终端电路。具有ESD保护功能的PMOS晶体管被放置在从信号端到输入缓冲器的线路上的信号节点和电源电压节点之间。此外，放置电压发生器电路以向PMOS晶体管的栅极提供参考电压。通过由电压发生器电路控制的参考电压，设置PMOS晶体管的源极漏极电阻。由此，除了ESD保护功能之外，还可以使PMOS晶体管起到终端电阻的作用，该电阻的电阻可以适应于传输线的特性阻抗，例如连接到信号端。

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