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1. 发明授权

US07902860B2 Semiconductor circuit, and computing device and communications device using the same 有权
标题翻译：半导体电路，以及使用它的计算设备和通信设备
公开(公告)号：US07902860B2
公开(公告)日：2011-03-08
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi Yamamoto , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译：在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路计算由工作点计算电路找到的工作点处的阻抗。阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。

2. 发明授权

US07772877B2 Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US07772877B2
公开(公告)日：2010-08-10
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，以提高预加重量的分辨率，而不增加功耗或电路面积。输出缓冲器包括延迟电路，反相器和输出缓冲器，以将逻辑信号传输到传输线，并根据传输线的信号衰减量产生在发送侧具有四种或更多种类型的信号电压的波形。输出缓冲器具有输出电阻的选择器和可变电阻部分，以根据可变电阻值的变化改变预加重量。逆变器被配置为选择要输入到输出缓冲器的信号，反转数据信号并通过选择器逻辑的选择信号调整抽头预加重量。

3. 发明授权

US07649381B2 Level conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US07649381B2
公开(公告)日：2010-01-19
申请号：US12000608
申请日：2007-12-14
申请人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
发明人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/018521
摘要： A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.
摘要翻译：一种能够实现低功率/高速操作并且抑制由于源电压和温度以及器件变化的变化而导致的输入/输出特性变化的电平转换电路。电平转换电路包括：源极跟随器电路，包括用于向其输入CML电平的AC信号的第一晶体管和向其输入控制电压的第二晶体管; 以及控制电压产生电路，用于产生要输入到第二晶体管的控制电压。控制电压产生电路包括：复制源跟随器电路，其是源极跟随器电路的副本，其包括用于输入CML电平的中心电压的第三晶体管和向其输入控制电压的第四晶体管; 以及控制控制电压的比较器，从而使复制源极跟随器的输出电压和CMOS电路的阈值电压相等。

4. 发明申请

US20080157816A1 Level conversion circuit 有权
标题翻译：电平转换电路
公开(公告)号：US20080157816A1
公开(公告)日：2008-07-03
申请号：US12000608
申请日：2007-12-14
申请人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
发明人： Hiroki Yamashita , Fumio Yuuki , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
IPC分类号： H03K19/094
CPC分类号： H03K19/094 , H03K19/018521
摘要： A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.
摘要翻译：一种能够实现低功率/高速操作并且抑制由于源电压和温度和器件变化的变化而导致的输入/输出特性变化的电平转换电路。电平转换电路包括：源极跟随器电路，包括用于向其输入CML电平的AC信号的第一晶体管和向其输入控制电压的第二晶体管; 以及控制电压产生电路，用于产生要输入到第二晶体管的控制电压。控制电压产生电路包括：复制源跟随器电路，其是源极跟随器电路的副本，其包括用于输入CML电平的中心电压的第三晶体管和向其输入控制电压的第四晶体管; 以及控制控制电压的比较器，从而使复制源极跟随器的输出电压和CMOS电路的阈值电压相等。

5. 发明申请

US20080159460A1 ADJUSTMENT METHOD, CIRCUIT, RECEIVER CIRCUIT AND TRANSMISSION EQUIPMENT OF WAVEFORM EQUALIZATION COEFFICIENT 有权
标题翻译：调整方法，电路，接收机电路和波形均衡系统的传输设备
公开(公告)号：US20080159460A1
公开(公告)日：2008-07-03
申请号：US11965783
申请日：2007-12-28
申请人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
发明人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
IPC分类号： H03D3/24
CPC分类号： H04L25/03885
摘要： In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.
摘要翻译：在波形均衡系数的调整方法中，仅在任意信号序列的情况下测量抖动和幅度之一并且调整波形均衡系数。特别地，使用除010信号或101信号之外的接收信号的信号，测量码反转时间。由于在使用这种信号的情况下的代码反转时间与传统技术相比变得更陡峭，所以可以减小波形均衡系数的调整时间。

6. 发明授权

US06856709B2 Optical modulation device 有权
标题翻译：光调制装置
公开(公告)号：US06856709B2
公开(公告)日：2005-02-15
申请号：US10112795
申请日：2002-03-28
申请人： Kouichi Uesaka , Takashi Suga , Hisaaki Kanai , Yoshinori Nagoya
发明人： Kouichi Uesaka , Takashi Suga , Hisaaki Kanai , Yoshinori Nagoya
IPC分类号： G02B6/12 , G02F1/01 , G02F1/015 , G02F1/035 , H01P3/08 , H01P5/08 , H04B10/00 , H04B10/25
CPC分类号： G02F1/0356 , H01P5/08
摘要： The provision of a coplanar waveguide coupled with a microstrip line with a transmission line substrate that is used between two functional units of different impedance characteristics allows the input and output impedance matching to be performed, the impedance matching between which coplanar waveguide and microstrip line is performed by the variation of the signal linewidth. It allows the transmission characteristics of the optical transmission device in high frequency band to improve.
摘要翻译：提供与具有传输线基板的微带线路耦合的传输线基板，其在不同阻抗特性的两个功能单元之间使用允许执行输入和输出阻抗匹配，执行共面波导和微带线之间的阻抗匹配通过信号线宽的变化。能够提高高频带内的光传输装置的传输特性。

7. 发明申请

US20090179666A1 OUTPUT BUFFER CIRCUIT, DIFFERENTIAL OUTPUT BUFFER CIRCUIT, OUTPUT BUFFER CIRCUIT HAVING REGULATION CIRCUIT AND REGULATION FUNCTION, AND TRANSMISSION METHOD 有权
标题翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路及传输方式
公开(公告)号：US20090179666A1
公开(公告)日：2009-07-16
申请号：US12343521
申请日：2008-12-24
申请人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
发明人： Norio Chujo , Keiichi Yamamoto , Hisaaki Kanai , Toru Yazaki
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H04L25/0278 , H04L25/028
摘要： An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance. The inverter 22 is configured to select a signal to be input into the output buffer 6 according to a selector logic, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
摘要翻译：输出缓冲电路，差分输出缓冲电路，具有调节电路和调节功能的输出缓冲电路以及传输方法，能够提高预加重量的分辨率而不增加功耗或电路面积，其中输出缓冲电路10具有包括延迟电路23，反相器22和输出缓冲器3〜7的功能，以将逻辑信号发送到传输线2，并在发送侧产生具有四种或更多种信号电压的波形根据传输线2的信号衰减量，输出缓冲器3具有导通电阻的可变电阻部分12，以根据可变电阻值的变化改变预加重量。输出缓冲器3具有前级上的选择器20和导通电阻的可变电阻部分12。反相器22被配置为根据选择器逻辑选择要输入到输出缓冲器6的信号，反转数据信号，并通过选择器逻辑的选择信号来调整抽头预加重量。

8. 发明申请

US20090085688A1 Semiconductor Circuit, and Computing Device and Communications Device Using the Same 有权
标题翻译：半导体电路和使用其的计算设备和通信设备
公开(公告)号：US20090085688A1
公开(公告)日：2009-04-02
申请号：US12145829
申请日：2008-06-25
申请人： Keiichi YAMAMOTO , Norio Chujo , Toru Yazaki , Hisaaki Kanai
发明人： Keiichi YAMAMOTO , Norio Chujo , Toru Yazaki , Hisaaki Kanai
IPC分类号： H03H11/30
CPC分类号： H03F3/3028 , H01L2924/19051 , H03F1/308 , H03F2200/447 , H03F2200/453 , H03K19/017581
摘要： In a semiconductor circuit, an impedance adjustment circuit having the characteristics same as those of a circuit having the nonlinear resistance characteristics is configured to include an operating point calculation circuit automatically calculating an operating point with a reference resistance through feedback control, and an impedance calculation circuit calculating the impedance at the operating point found by the operating point calculation circuit. The impedance adjustment circuit is also provided with an impedance determination circuit that determines whether or not the impedance found by the impedance calculation circuit is in a predetermined range. These components, i.e., the operating point calculation circuit, the impedance calculation circuit, and the impedance determination circuit, are provided each two for High-side and Low-side impedance adjustment use.
摘要翻译：在半导体电路中，具有与具有非线性电阻特性的电路相同特性的阻抗调整电路被配置为包括工作点计算电路，通过反馈控制自动计算具有参考电阻的工作点，以及阻抗计算电路计算由工作点计算电路找到的工作点处的阻抗。阻抗调整电路还设置有阻抗确定电路，其确定由阻抗计算电路发现的阻抗是否在预定范围内。这两个部件，即工作点计算电路，阻抗计算电路和阻抗确定电路，每两个用于高侧和低侧阻抗调节。

9. 发明申请

US20070184687A1 Circuit board provided with digging depth detection structure and transmission device with the same mounted 审中-公开
标题翻译：电路板配有挖掘深度检测结构和传输装置相同的安装
公开(公告)号：US20070184687A1
公开(公告)日：2007-08-09
申请号：US11657462
申请日：2007-01-25
申请人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
发明人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
IPC分类号： H05K1/00
CPC分类号： H05K1/0268 , H05K1/0237 , H05K3/0047 , H05K3/429 , H05K2203/0207 , H05K2203/0242 , H05K2203/163 , H05K2203/175
摘要： One of a group which is located on the side of a main surface of the circuit board than the one conductive layer of the plurality of conductive layers is used as a terminal to detect the digging depth of the through hole, and the digging of the through hole is stopped according to the change of the conductive state between the detection terminal and the through hole (or the one conductive layer which is electrically connected to this). A circuit board is formed so that the detection terminal in a group of the plurality of conductive layers contacts with the drill which dig the through hole and a group of the conductive layers except the detection terminal does not contact with the drill, respectively.
摘要翻译：使用位于电路板的主表面侧的多个导电层的一个导电层中的一个作为端子来检测通孔的挖掘深度，并且挖掘通孔根据检测端子和通孔（或与其电连接的一个导电层）之间的导电状态的变化来停止孔。形成电路板，使得多个导电层中的一组中的检测端子与钻孔相接触，钻头分别钻出通孔，除了检测端子之外的一组导电层不与钻头接触。

10. 发明授权

US07965765B2 Adjustment method, circuit, receiver circuit and transmission equipment of waveform equalization coefficient 有权
标题翻译：调整方法，电路，接收机电路和传输设备的波形均衡系数
公开(公告)号：US07965765B2
公开(公告)日：2011-06-21
申请号：US11965783
申请日：2007-12-28
申请人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
发明人： Hisaaki Kanai , Norio Chujo , Masayoshi Yagyu
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.
摘要翻译：在波形均衡系数的调整方法中，仅在任意信号序列的情况下测量抖动和幅度之一并且调整波形均衡系数。特别地，使用除010信号或101信号之外的接收信号的信号，测量码反转时间。由于在使用这种信号的情况下的代码反转时间与传统技术相比变得更陡峭，所以可以减小波形均衡系数的调整时间。

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